> 
> The problem is (as far as it has been diagnosed) in PCI DMA, not
> in the IDE part of the chip. It's just that the IDE controller
> is the most likely candidate to do busmastering DMA in the
> most usual system configurations.
> 

From ECS K7VZA v3.0 motherboard BIOS release notes:

"5. Add a new item "PCI Master Bus TimeOut Control"to
                                       fix 686B ATA-100 issue"


And "PCI Master Bus Time-Out" option in fact appeared in BIOS Advanced 
Chipset Setup. It defaults to 1 (32 PCICLKs) in both optimal and fail-safe 
settings. All other features like PCI delayed transaction, bursting or 
master read caching are _still on_ in optimal settings.

The setting is described in chipset manual: "force into arbitration after 
certain period of time". Values: 0 - dissabled (default), 1-15 - time in
32 PCICLKs increments. I don't know what this exactly means (will it break 
every burst after 32 PCICLKs?) and how this can fix the problem. Any ideas?


Greetings,

	Witold J. Wnuk