On Sat, Sep 09, 2000 at 12:35:46AM +0200, Manuel Bouyer wrote:

 > uh, I got the same close results (i.e no perf improvements) on my celeron 500
 > at home, which has this:
 > cpu0: features 183f9ff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR>
 > cpu0: features 183f9ff<PGE,MCA,CMOV,FGPAT,PSE36,MMX,FXSR>
 > 
 > I guess all what's needed is here ...
 > 
 > Either something didn't get enabled (althout I checked that LARGEPAGE is
 > defined), or this isn't as good as it looked :)

If you're running userspace-intensive code, the boost is likely to be
less.  In my particular application, I'm going to be running mostly
system/interrupt time (around 80% combined system/interrupt time), so
having the kernel text mapped w/ only 1 ITLB entry is going to be a big
help.

I'm also working on some changes to the pool allocator which will allow
for "pages reserved for pools", with hooks to allow those reserved pages
to be mapped using large DTLB entries.  In my target application, using
such reserved-page pools for e.g. mbufs/clusters could show a fair amount
of improvement in ip forwarding/ipsec performance.  We'll see, I haven't
run my experiments yet.

-- 
        -- Jason R. Thorpe <thorpej@zembu.com>