Subject: Re: Interrupt handling
To: John F. Woods <firstname.lastname@example.org>
From: VaX#n8 <email@example.com>
Date: 11/08/1994 15:45:41
While really really bored, John F. Woods wrote:
> There's no reason why the kernel won't support multiple devices on the
> same interrupt priority level, as long as each device has its own interrupt
Is this truly necessary?
Multiple devices on the same IRQ do work w/o vectored interrupts, unless
I misunderstand; you simply have to poll relevant devices to determine
which one generated the interrupt.
> interrupt vectors). Then Intel family, of course, ties the priority
> to the vector (if I recall correctly, the processor itself doesn't even
> have a "vector number" or even a priority level, it has to poll an
> external chip to find out the priority level, which directly implies
> a vector number). Other processor families may have different behaviors.
True. It has one "interrupt" pinout and a NMI pinout. The Intel 8259 has
eight IRQ ins, and does the prioritizing with internal logic. PC AT's and
above (e.g. everything you might want to use) have two 8259's, one
cascaded through the other on it's IRQ2.
Moto's is a much nicer design all around. Although IBM/Intel could have
done some cool external logic instead of just using standard 8259's anyway.
Note that many games (DooM?!) and other apps still don't support the higher
level (cascaded) interrupt levels. Shame on them.
> That said, I believe that some devices are able to share interrupts, but
> the device has to be carefully designed to make that work (easy to poll
> for interrupt status, etc.). A randomly chosen ISA bus board will not
> necessarily be able to make that work. (I seem to recall there's a version
> of the COM device driver that shares interrupts.)
Doubly true. Most of the time you will want mboard support for unique
board identification; I believe EISA does this (e.g. you can address
the board in slot two, for example). However, I'm not sure of the details.
The microsloth plug-and-plagerize, which my friend is designing a board for,
uses some algorithm to uniquely identify a board on the ISA bus. However,
each board must have a special unique ID bitstring... so we come back to new
hardware again. And it takes a while, since you've got to narrow down each
board with a (really stupid) identification protocol.
"Does your ID string begin with 0?" "Is the next digit a 0?" "Is the next
a zero?" "no? Okay, how about a 1?" etc. Each board must have logic to
recognize these signals and assert itself on the bus in response, etc.
You're probably better off abandoning your old mboards and just plunking down
the ducats for a better bus if you're gonna buy new HW anyway.
Not that I've gotten around to buying any EISA device adapters yet :)
VaX#n8 (vak-sa-nate) - n, CS senior++ and Unix junkie - firstname.lastname@example.org
Just the vax-man. Read my MIPS, no new VAXes! - PGP key on request