Subject: Re: Vr4131 cache configuration
To: TAKEMURA Shin <firstname.lastname@example.org>
From: TAKEMURA Shin <email@example.com>
Date: 12/23/2001 22:08:30
Thank you for your comments.
I've commited. Please check it.
updated files are:
----- Original Message -----
From: "TAKEMURA Shin" <firstname.lastname@example.org>
Sent: Sunday, December 16, 2001 11:40 PM
Subject: Vr4131 cache configuration
> I'm working on NEC's new MIPS CPU Vr4131.
> Vr4131 has 2-way set-associative cache though Vr4131's
> processor revision number on COP0 is same as other
> Vr41xx which has direct-mapped cache. So, you must
> distinguish Vr4131 from other Vr41xx in mips_config_cache().
> You can use highest bit of MIPS_PRID_REV field.
> I've made the patch (attached). I'd like to commit the patch
> if no one objects.