Subject: Re: Vr4131 cache configuration
To: TAKEMURA Shin <takemura@netbsd.org>
From: enami tsugutomo <enami@but-b.or.jp>
List: port-hpcmips
Date: 12/17/2001 08:01:39
> I've made the patch (attached). I'd like to commit the patch
> if no one objects.
	    :
>         case MIPS_R4000:
>         case MIPS_R4100:
>         case MIPS_R4300:
> + #ifdef MIPS3_4100
> +               /*
> +                * Vr4131 has cpu_id=0x0c80
> +                * and R4600 style 2-way set-associative cache
> +                */
> +               if (!(MIPS_PRID_IMPL(cpu_id) == MIPS_R4100 &&
> +                   (MIPS_PRID_REV(cpu_id) & 0x80))) {
> + #endif
>                 mips_picache_ways = 1;
>                 mips_pdcache_ways = 1;
> <snipped>
>                 /* Virtually-indexed cache; no use for colors. */
>                 break;
> + #ifdef MIPS3_4100
> +               }
> +               /* fall through if CPU is Vr4131 */
> + #endif
> 
>         case MIPS_R4600:
>         case MIPS_RM5200:

I think it is better to use `goto' here (like below, but untested) to
express that Vr4131 case is a special case.  The <snipped> code is
rather large.

enami.
Index: cache.c
===================================================================
RCS file: /cvsroot/syssrc/sys/arch/mips/mips/cache.c,v
retrieving revision 1.5
diff -u -r1.5 cache.c
--- cache.c	2001/11/23 06:21:50	1.5
+++ cache.c	2001/12/16 22:54:59
@@ -284,8 +284,15 @@
 #endif /* MIPS1 */
 
 #ifdef MIPS3
-	case MIPS_R4000:
 	case MIPS_R4100:
+		/*
+		 * Vr4131 has cpu_id=0x0c80
+		 * R4600 style 2-way set-associative cache
+		 */
+		if ((MIPS_PRID_REV(cpu_id) & 0x80) != 0)
+			goto primary_cache_is_2way;
+		/* FALLTHROUGH */
+	case MIPS_R4000:
 	case MIPS_R4300:
 		mips_picache_ways = 1;
 		mips_pdcache_ways = 1;
@@ -360,6 +367,7 @@
 	case MIPS_R5000:
 #endif
 	case MIPS_RM5200:
+ primary_cache_is_2way:
 		mips_picache_ways = 2;
 		mips_pdcache_ways = 2;