Herb Peyerl wrote:
> 
> mike smith <miff@spam.frisbee.net.au>  wrote:
>  > >     pic         base+0xe0
>  >
>  > No details on this one? 8(
> 
>         picbase+0x0             upper interrupt enable reg.
>         picbase+0x4             lower interrupt enable reg.

Am I getting too demanding yet?  How about bit assignments
for thes registers?  So far I have the four internal 
SIOs on the 4 MSb's of these enables; how about the ISA
interrupt; does it rate a bit here somewhere?  The timer?

>         picbase+0x18            interrupt vector register
>         picbase+0x1c            interrupt ack (?)

Yeow! Them's the good stuff; the IVR tells me that this
part can autovector, which might be handy.  The ack register
will take some playing with; it might take a binary value
or bit pattern write, or a read or write to acknowledge all
of the pending interrupts (erk, race-o-rama).
 
Any idea which IPL this part is normally on?

> as far as pio goes:
> 
>         piobase+0x0             parallel input register
>         piobase+0x4             input polarity register
>         piobase+0x8             input edge/level register

Teaser, I'm sure.  Where's the pio register?  Wonder if it
actually goes anywhere on the 425?

--
Mike Smith  *BSD hack  Unix hardware collector
The question "why are the fundamental laws of nature mathematical"
invites the trivial response "because we define as fundamental those
laws which are mathematical".  Paul Davies, _The_Mind_of_God_