Izumi Tsutsui wrote:
> In article <4405F49B.1020201@tadpole.com>
> garrett_damore@tadpole.com wrote:
>
>   
>> I *think* what is happening is that the interrupt handlers are coming
>> and going during boot flow.
>>     
>
> What is "during boot flow"?
> Before mountroot, or during rc.d processes?
>   
Before mountroot.  But I've seen it on both sides.
> I have one concern that clock interrupt (INT5) shouldn't be
> enabled until cpu_initclocks() is called, but I'm not sure
> if that could cause your problem.
>   
Hmm.. that might be a good point.
>   
>> Wed Mar  1 11:20:07 PST 2006
>> trap: TLB miss (load or instr. fetch) in kernel mode
>> status=0x2, cause=0x800408, epc=0x802d7e14, vaddr=0x1040002c
>> curlwp == NULL ksp=0xc0080d80
>> Stopped at      netbsd:aucomintr+0x88:  lw      v0,44(s2)
>>     
>
> Hmm, how can the address 0x104000xx be passed for a pointer?
> MIPS_PHYS_TO_KSEG1() is missed somewhere?
>   
Maybe.
> (btw ic0_base and ic1_base in au_icu.c should be vaddr_t,
>  not bus_addr_t, I think)
>   
I'll take a look at it.

    -- Garrett
> ---
> Izumi Tsutsui
>   


-- 
Garrett D'Amore, Principal Software Engineer
Tadpole Computer / Computing Technologies Division,
General Dynamics C4 Systems
http://www.tadpolecomputer.com/
Phone: 951 325-2134  Fax: 951 325-2191