Subject: PCI and Endianness on the Au15XX
To: Simon Burge <simonb@wasabisystems.com>
From: Garrett D'Amore <garrett_damore@tadpole.com>
List: port-evbmips
Date: 11/23/2005 23:06:52
Well, I've done a lot of testing lately of my PCI code and the Alchemy
Au1550 and Au1500 onchip PCI controllers.

I'm not too happy with my findings.  Basically, everything works fine in
little endian mode.  In big endian mode, I cannot get correct results
with DMA.  PIO works fine.  Devices that have onboard endian swapping
and autodetect in their drivers (e.g. ath, maybe others) seem to work OK.

It seems that no matter how I program the chip, it doesn't want to do
"the right thing", which is stream bytes from the device into my DMA region.

I have requested help from AMD on the matter, but right not I'm not too
optimistic -- I kind of expect them to say "just run it little endian".

So, the question becomes what to do about this.  I can leave PCI
enabled, with the caveat that most DMA mastering devices will not work
if the part is big-endian.  Or I can fail to attach the PCI bus if in
big-endian mode (which is safe, but may be limiting in some configs.)

Are there any other thoughts on the matter?  I'd love to hear from
anyone with experience or suggestions relating to PCI and endianness
with these parts, but right now I suspect that the number of such folks
is pretty small, and likely even zero (not including myself) for NetBSD.

The second question is whether I should wait for an answer from AMD
(which could take a while) before submitting my changes, which at least
work well in little endian mode.

Thoughts?

-- 
Garrett D'Amore                          http://www.tadpolecomputer.com/
Sr. Staff Engineer          Extending the Power of 64-bit UNIX Computing
Tadpole Computer, Inc.                             Phone: (951) 325-2134