kiyohara@kk.iij4u.or.jp wrote:

> My Qube2 panicing when boot time since May 31 2006.  Because that has
> shared IRQs at PCI-card.  However current icu_intr_establish() denied
> sharing IRQs.  (However, I feel old icu_intr_establish() strange... ;-)

It should be trivial to implement shared IRQ support on ICU (aka PIC).
Just prepare a intrtab LIST and check IST types on the intr_establish()
function like sys/arch/algor/pci/pcib.c does.

But I didn't implement it because I was not sure it was
really required on any cobalt machines.

>       uhci2: interrupting at irq 0
>       ehci0: interrupting at irq 0
>       fwohci0: interrupting at irq 0

All these devices are behind the PCI-PCI bridge, but
what interrupt PINs (A-D) are used for their interrupts?
"irq 0" just means "invalid," which is returned from
current sys/arch/cobalt/pci/pci_machdep.c:pci_intr_map().
It just returns "line" values, but I don't think these
values for PIN B-D are initilized properly by the firmware,
nor pci_conf_interrupt().

So, before implemente shared IRQ support code, we should
know hardware specification around cobalt PCI, i.e.
we should know which IRQ pins each PIN A-D lines are
connected to. If each PIN A-D lines of the PCI slot
are connected to independent ICU irq pins, we don't
have to have shared irq support at all.

According to PCI spec, single PCI card could share the
same PIN for multiple devices, but I think such
configuration is very rare.
---
Izumi Tsutsui