mk@kilbi.de wrote:

>     Izumi> Could you try a kernel without patch against
>     Izumi> cobalt/dev/gt.c?
> 
> I'm running a kernel w/o the gt.c patch flawlessly so far, no obvious
> negative effects. I will report otherwise...

Umm, I should have tried benchmark on my RaQ2 first.

It seems setting the GT64x11 timeout and retry register
improves disk I/O performance on my RaQ2 at least with bonnie:

on COBALT_TEST-20060518 kernel:
---
              -------Sequential Output-------- ---Sequential Input-- --Random--
              -Per Char- --Block--- -Rewrite-- -Per Char- --Block--- --Seeks---
Machine    MB K/sec %CPU K/sec %CPU K/sec %CPU K/sec %CPU K/sec %CPU  /sec %CPU
          100  3798 94.2  4159 61.9  3539 82.3  4565 98.9 13901 99.9 407.3 89.0
---

on the same COBALT_TEST kernel with the attached gt.c patch:
---
              -------Sequential Output-------- ---Sequential Input-- --Random--
              -Per Char- --Block--- -Rewrite-- -Per Char- --Block--- --Seeks---
Machine    MB K/sec %CPU K/sec %CPU K/sec %CPU K/sec %CPU K/sec %CPU  /sec %CPU
          100  4301 96.1  7637 81.5  6030 92.0  4767 98.7 14102 99.8 777.1 99.0
---


Index: dev/gt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/dev/gt.c,v
retrieving revision 1.17
diff -u -r1.17 gt.c
--- dev/gt.c	21 Apr 2006 19:04:57 -0000	1.17
+++ dev/gt.c	19 May 2006 14:40:05 -0000
@@ -114,6 +114,8 @@
 	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND,
 	    (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND) &
 	    ~PCI_SYNCMODE) | PCI_PCLK_HIGH);
+	bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_TIMEOUT_RETRY,
+	    0xff << PCI_RETRYCTR_SHIFT | 0xff << PCI_TIMEOUT1_SHIFT | 0xff);
 
 #if NPCI > 0
 	pc = &sc->sc_pc;

---

viaide0 at pci0 dev 9 function 1
viaide0: VIA Technologies VT82C586 (Apollo VP) ATA33 controller
viaide0: bus-master DMA support present
viaide0: primary channel configured to compatibility mode
viaide0: primary channel interrupting at irq 14
atabus0 at viaide0 channel 0
viaide0: secondary channel configured to compatibility mode
viaide0: secondary channel interrupting at irq 15
atabus1 at viaide0 channel 1
 :
wd0 at atabus0 drive 0: <IBM-DTTA-351680>
wd0: drive supports 16-sector PIO transfers, LBA addressing
wd0: 16124 MB, 32760 cyl, 16 head, 63 sec, 512 bytes/sect x 33022080 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 2 (Ultra/33)
wd0(viaide0:0:0): using PIO mode 4, Ultra-DMA mode 2 (Ultra/33) (using DMA)

---
Izumi Tsutsui