Subject: Re: "pmap_unwire: wiring ... didn't change!"
To: Simon Burge <>
From: Markus W Kilbinger <>
List: port-cobalt
Date: 03/07/2005 23:53:33
>>>>> "Simon" == Simon Burge <> writes:

    Simon> Thinking about this a little, I guess we could just map all
    Simon> TLB pages uncached if we want to mostly disable caches.
    Simon> Could someone try changing the this line in
    Simon> sys/arch/mips/include/mips3_pte.h (around line 135):

    Simon>   #define MIPS3_DEFAULT_PG_CACHED MIPS3_CCA_TO_PG(3)

    Simon> to 

    Simon>   #define MIPS3_DEFAULT_PG_CACHED MIPS3_CCA_TO_PG(2)

    Simon> For the RM5200, using 1 or 2 will also select write-through
    Simon> modes so that may well be worth trying too.

I've tested this on my qube2 (RM5231) with following values:


according to
with the meaning of:

  TLB CCA field definitions

  0   cacheable, noncoherent, write-thru, no-write-allocate
  1   cacheable, noncoherent, write-thru, write-allocate
  2   uncached

I've seen quite regular data corruption in _all_ three (3) cases! ...
whereas '2' is the slowest 'mode' (about a 10th of the normal system
speed). Modes '1' and '0' yield about half of the normal system speed.