Subject: Re: 2.0 installation issues on RaQ2
To: None <port-cobalt@NetBSD.org>
From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
List: port-cobalt
Date: 02/26/2005 00:59:04
In article <200502251053.j1PArCH08671@smtp.pop3now.com>
jurrie@sackheads.org wrote:
> I see there are some additional items in the standard kernel compared to
> the 1.6.1 kernel. Does anyone have a 2.0 kernel that'll boot on a RaQ2
> (or Qube2) that I can try? Any other ideas?
PCI siop doesn't work with 2.0-release kernels.
Try attached diff (for netbsd-2 branch), or compiled binary:
http://www.ceres.dti.ne.jp/~tsutsui/netbsd/netbsd-cobalt-pciconf-20050225.gz
---
Izumi Tsutsui
tsutsui@ceres.dti.ne.jp
Index: sys/arch/cobalt/cobalt/clock.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/cobalt/clock.c,v
retrieving revision 1.6
diff -u -r1.6 clock.c
--- sys/arch/cobalt/cobalt/clock.c 15 Jul 2003 01:29:22 -0000 1.6
+++ sys/arch/cobalt/cobalt/clock.c 25 Feb 2005 15:53:31 -0000
@@ -38,16 +38,23 @@
#include <dev/ic/mc146818reg.h>
-void cpu_initclocks(void);
-void inittodr(time_t);
-void resettodr(void);
-void setstatclockrate(int);
+#include <cobalt/cobalt/clockvar.h>
+
+void (*timer_start)(void *);
+long (*timer_read)(void *);
+void *timer_cookie;
void
cpu_initclocks()
{
+
inittodr(0);
+ /* start timer */
+ if (timer_start == NULL)
+ panic("cpu_initclocks(): no timer configured");
+ (*timer_start)(timer_cookie);
+
return;
}
@@ -133,3 +140,32 @@
return;
}
+
+void
+microtime(struct timeval *tvp)
+{
+ int s;
+ static struct timeval lasttime;
+
+ s = splclock();
+
+ *tvp = time;
+
+ if (timer_read)
+ tvp->tv_usec += (*timer_read)(timer_cookie);
+
+ if (tvp->tv_usec >= 1000000) {
+ tvp->tv_usec -= 1000000;
+ tvp->tv_sec++;
+ }
+
+ if (tvp->tv_sec == lasttime.tv_sec &&
+ tvp->tv_usec <= lasttime.tv_usec &&
+ (tvp->tv_usec = lasttime.tv_usec + 1) >= 1000000) {
+ tvp->tv_sec++;
+ tvp->tv_usec -= 1000000;
+ }
+
+ lasttime = *tvp;
+ splx(s);
+}
Index: sys/arch/cobalt/cobalt/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/cobalt/machdep.c,v
retrieving revision 1.50.2.1
diff -u -r1.50.2.1 machdep.c
--- sys/arch/cobalt/cobalt/machdep.c 11 Apr 2004 04:01:33 -0000 1.50.2.1
+++ sys/arch/cobalt/cobalt/machdep.c 25 Feb 2005 15:53:31 -0000
@@ -355,36 +355,6 @@
for (;;);
}
-void
-microtime(tvp)
- struct timeval *tvp;
-{
- int s = splclock();
- static struct timeval lasttime;
- u_int32_t counter0;
-
- *tvp = time;
-
- counter0 = *(volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x14000850);
-
- /*
- * XXX
- */
-
- counter0 /= 50;
- counter0 %= 10000;
-
- if (counter0 > 9999) {
- counter0 = 9999;
- }
-
- tvp->tv_usec -= tvp->tv_usec % 10000;
- tvp->tv_usec += 10000 - counter0;
-
- lasttime = *tvp;
- splx(s);
-}
-
unsigned long cpuspeed;
__inline void
Index: sys/arch/cobalt/cobalt/mainbus.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/cobalt/mainbus.c,v
retrieving revision 1.8
diff -u -r1.8 mainbus.c
--- sys/arch/cobalt/cobalt/mainbus.c 12 Sep 2003 14:59:13 -0000 1.8
+++ sys/arch/cobalt/cobalt/mainbus.c 25 Feb 2005 15:53:31 -0000
@@ -32,14 +32,11 @@
#include <sys/systm.h>
#include <sys/device.h>
-#include <dev/pci/pcivar.h>
-
#include <mips/cpuregs.h>
#include <machine/autoconf.h>
#include "locators.h"
-#include "pci.h"
static int mainbus_match(struct device *, struct cfdata *, void *);
static void mainbus_attach(struct device *, struct device *, void *);
Index: sys/arch/cobalt/conf/GENERIC
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/conf/GENERIC,v
retrieving revision 1.54.2.3
diff -u -r1.54.2.3 GENERIC
--- sys/arch/cobalt/conf/GENERIC 15 Jul 2004 20:15:20 -0000 1.54.2.3
+++ sys/arch/cobalt/conf/GENERIC 25 Feb 2005 15:53:31 -0000
@@ -156,6 +156,8 @@
pchb* at pci? dev ? function ?
pcib* at pci? dev ? function ?
+options PCI_NETBSD_CONFIGURE
+
# Cryptographic Devices
# PCI cryptographic devices
Index: sys/arch/cobalt/dev/gt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/dev/gt.c,v
retrieving revision 1.9
diff -u -r1.9 gt.c
--- sys/arch/cobalt/dev/gt.c 15 Jul 2003 01:29:23 -0000 1.9
+++ sys/arch/cobalt/dev/gt.c 25 Feb 2005 15:53:31 -0000
@@ -28,6 +28,9 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.9 2003/07/15 01:29:23 lukem Exp $");
+#include "opt_pci.h"
+#include "pci.h"
+
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
@@ -42,21 +45,37 @@
#include <sys/syslog.h>
#include <sys/types.h>
#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/extent.h>
-#include <machine/intr.h>
+#include <machine/autoconf.h>
#include <machine/bus.h>
+#include <machine/intr.h>
#include <dev/pci/pcivar.h>
-#include "pci.h"
+#ifdef PCI_NETBSD_CONFIGURE
+#include <dev/pci/pciconf.h>
+#endif
+
+#include <cobalt/cobalt/clockvar.h>
+#include <cobalt/dev/gtreg.h>
struct gt_softc {
struct device sc_dev;
+
+ bus_space_tag_t sc_bst;
+ bus_space_handle_t sc_bsh;
+ struct cobalt_pci_chipset sc_pc;
};
static int gt_match(struct device *, struct cfdata *, void *);
static void gt_attach(struct device *, struct device *, void *);
static int gt_print(void *aux, const char *pnp);
+static void gt_timer_init(struct gt_softc *sc);
+static void gt_timer0_init(void *);
+static long gt_timer0_read(void *);
+
CFATTACH_DECL(gt, sizeof(struct gt_softc),
gt_match, gt_attach, NULL, NULL);
@@ -69,21 +88,48 @@
return 1;
}
+#define GT_REG_REGION 0x1000
+
static void
gt_attach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
+ struct mainbus_attach_args *ma = aux;
+ struct gt_softc *sc = (void *)self;
+#if NPCI > 0
+ pci_chipset_tag_t pc;
struct pcibus_attach_args pba;
+#endif
+
+ sc->sc_bst = ma->ma_iot;
+ if (bus_space_map(sc->sc_bst, ma->ma_addr, GT_REG_REGION,
+ 0, &sc->sc_bsh)) {
+ printf(": unable to map GT64111 registers\n");
+ return;
+ }
printf("\n");
- /* XXX */
- *((volatile u_int32_t *)0xb4000c00) =
- (*((volatile u_int32_t *)0xb4000c00) & ~0x6) | 0x2;
+ gt_timer_init(sc);
+
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND,
+ (bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_PCI_COMMAND) &
+ ~PCI_SYNCMODE) | PCI_PCLK_HIGH);
#if NPCI > 0
+ pc = &sc->sc_pc;
+ pc->pc_bst = sc->sc_bst;
+ pc->pc_bsh = sc->sc_bsh;
+
+#ifdef PCI_NETBSD_CONFIGURE
+ pc->pc_ioext = extent_create("pciio", 0x10100000, 0x11ffffff,
+ M_DEVBUF, NULL, 0, EX_NOWAIT);
+ pc->pc_memext = extent_create("pcimem", 0x12000000, 0x13ffffff,
+ M_DEVBUF, NULL, 0, EX_NOWAIT);
+ pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0, 0);
+#endif
pba.pba_busname = "pci";
pba.pba_dmat = &pci_bus_dma_tag;
pba.pba_dmat64 = NULL;
@@ -92,9 +138,9 @@
pba.pba_bridgetag = NULL;
pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
PCI_FLAGS_MRL_OKAY | /*PCI_FLAGS_MRM_OKAY|*/ PCI_FLAGS_MWI_OKAY;
+ pba.pba_pc = pc;
config_found(self, &pba, gt_print);
#endif
- return;
}
static int
@@ -105,3 +151,50 @@
/* XXX */
return 0;
}
+
+static void
+gt_timer_init(struct gt_softc *sc)
+{
+
+ /* stop timer0 */
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL,
+ bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) & ~ENTC0);
+
+ timer_start = gt_timer0_init;
+ timer_read = gt_timer0_read;
+ timer_cookie = sc;
+}
+
+#define TIMER0_INIT_VALUE 500000
+
+static void
+gt_timer0_init(void *cookie)
+{
+ struct gt_softc *sc = cookie;
+
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh,
+ GT_TIMER_COUNTER0, TIMER0_INIT_VALUE);
+ /* start timer0 */
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL,
+ bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_CTRL) | ENTC0);
+}
+
+static long
+gt_timer0_read(void *cookie)
+{
+ struct gt_softc *sc = cookie;
+ uint32_t counter0;
+
+ counter0 = bus_space_read_4(sc->sc_bst, sc->sc_bsh, GT_TIMER_COUNTER0);
+ counter0 = TIMER0_INIT_VALUE - counter0;
+#if 0
+ counter /= 50;
+#else
+ /*
+ * From pmax/pmax/dec_3min.c:
+ * 1/64 + 1/256 + 1/2048 = 41/2048 = 1/49.9512...
+ */
+ counter0 = (counter0 >> 6) + (counter0 >> 8) + (counter0 >> 11);
+#endif
+ return counter0;
+}
Index: sys/arch/cobalt/include/pci_machdep.h
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/include/pci_machdep.h,v
retrieving revision 1.5
diff -u -r1.5 pci_machdep.h
--- sys/arch/cobalt/include/pci_machdep.h 15 May 2002 19:23:53 -0000 1.5
+++ sys/arch/cobalt/include/pci_machdep.h 25 Feb 2005 15:53:31 -0000
@@ -34,6 +34,7 @@
* Machine-specific definitions for PCI autoconfiguration.
*/
#define __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
+#define __HAVE_PCI_CONF_HOOK
/*
* Forward declarations.
@@ -50,10 +51,18 @@
/*
* Types provided to machine-independent PCI code
*/
-typedef void *pci_chipset_tag_t;
+typedef struct cobalt_pci_chipset *pci_chipset_tag_t;
typedef u_int32_t pcitag_t;
typedef int pci_intr_handle_t;
+struct cobalt_pci_chipset {
+ bus_space_tag_t pc_bst; /* bus space tag for PCICFG regs */
+ bus_space_handle_t pc_bsh; /* bus space handle for PCICFG regs */
+
+ struct extent *pc_memext; /* PCI memory extent */
+ struct extent *pc_ioext; /* PCI I/O extent */
+};
+
/*
* Functions provided to machine-independent PCI code.
*/
@@ -72,6 +81,9 @@
void *pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
int, int (*)(void *), void *);
void pci_intr_disestablish(pci_chipset_tag_t, void *);
+void pci_conf_interrupt(pci_chipset_tag_t, int, int, int, int,
+ int *);
+int pci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t);
#define pci_enumerate_bus(sc, m, p) \
pci_enumerate_bus_generic((sc), (m), (p))
Index: sys/arch/cobalt/pci/pci_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/pci/pci_machdep.c,v
retrieving revision 1.15
diff -u -r1.15 pci_machdep.c
--- sys/arch/cobalt/pci/pci_machdep.c 12 Sep 2003 17:55:52 -0000 1.15
+++ sys/arch/cobalt/pci/pci_machdep.c 25 Feb 2005 15:53:31 -0000
@@ -34,6 +34,7 @@
#include <sys/systm.h>
#include <sys/errno.h>
#include <sys/device.h>
+#include <sys/extent.h>
#define _COBALT_BUS_DMA_PRIVATE
#include <machine/bus.h>
@@ -42,6 +43,9 @@
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcidevs.h>
+#include <dev/pci/pciconf.h>
+
+#include <cobalt/dev/gtreg.h>
/*
* PCI doesn't have any special needs; just use
@@ -103,9 +107,6 @@
*fp = (tag >> 8) & 0x07;
}
-#define PCI_CFG_ADDR ((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x14000cf8))
-#define PCI_CFG_DATA ((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x14000cfc))
-
pcireg_t
pci_conf_read(pc, tag, reg)
pci_chipset_tag_t pc;
@@ -128,9 +129,10 @@
if (bus == 0 && dev == 31)
return 0;
- *PCI_CFG_ADDR = 0x80000000 | tag | reg;
- data = *PCI_CFG_DATA;
- *PCI_CFG_ADDR = 0;
+ bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR,
+ 0x80000000 | tag | reg);
+ data = bus_space_read_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_DATA);
+ bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR, 0);
return data;
}
@@ -142,11 +144,11 @@
int reg;
pcireg_t data;
{
- *PCI_CFG_ADDR = 0x80000000 | tag | reg;
- *PCI_CFG_DATA = data;
- *PCI_CFG_ADDR = 0;
- return;
+ bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR,
+ 0x80000000 | tag | reg);
+ bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_DATA, data);
+ bus_space_write_4(pc->pc_bst, pc->pc_bsh, GT_PCICFG_ADDR, 0);
}
int
@@ -224,3 +226,28 @@
cpu_intr_disestablish(cookie);
icu_intr_disestablish(cookie);
}
+
+void
+pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz,
+ int *iline)
+{
+
+ /* not yet... */
+}
+
+int
+pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
+{
+
+ /* Don't configure the bridge and PCI probe. */
+ if (PCI_VENDOR(id) == PCI_VENDOR_GALILEO &&
+ PCI_PRODUCT(id) == PCI_PRODUCT_GALILEO_GT64011)
+ return 0;
+
+ /* Don't configure device 9 */
+ if (dev == 9)
+ return 0;
+
+ return PCI_CONF_ALL & ~(PCI_CONF_MAP_ROM |
+ PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE);
+}
Index: sys/dev/pci/pciconf.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pciconf.c,v
retrieving revision 1.23
diff -u -r1.23 pciconf.c
--- sys/dev/pci/pciconf.c 17 Mar 2004 20:27:57 -0000 1.23
+++ sys/dev/pci/pciconf.c 25 Feb 2005 15:53:32 -0000
@@ -705,10 +705,6 @@
PRIu64 " req)\n", pi->size);
return -1;
}
- if (!pb->io_32bit && pi->address > 0xFFFF) {
- pi->address = 0;
- pd->enable = 0;
- }
if (pd->ppb && pi->reg == 0) {
pd->ppb->ioext = extent_create("pciconf", pi->address,
pi->address + pi->size, M_DEVBUF, NULL, 0,
@@ -721,7 +717,12 @@
}
continue;
}
- pd->enable |= PCI_CONF_ENABLE_IO;
+ if (!pb->io_32bit && pi->address > 0xFFFF) {
+ pi->address = 0;
+ pd->enable &= ~PCI_CONF_ENABLE_IO;
+ } else {
+ pd->enable |= PCI_CONF_ENABLE_IO;
+ }
if (pci_conf_debug) {
print_tag(pd->pc, pd->tag);
printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64
@@ -775,7 +776,7 @@
if (pm->prefetch && !pb->pmem_64bit &&
pm->address > 0xFFFFFFFFULL) {
pm->address = 0;
- pd->enable = 0;
+ pd->enable &= ~PCI_CONF_ENABLE_MEM;
} else {
pd->enable |= PCI_CONF_ENABLE_MEM;
}
@@ -1005,7 +1006,10 @@
class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG);
misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG);
cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
- cmd |= PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE;
+ if (pd->enable & PCI_CONF_ENABLE_PARITY)
+ cmd |= PCI_COMMAND_PARITY_ENABLE;
+ if (pd->enable & PCI_CONF_ENABLE_SERR)
+ cmd |= PCI_COMMAND_SERR_ENABLE;
if (pb->fast_b2b)
cmd |= PCI_COMMAND_BACKTOBACK_ENABLE;
if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
@@ -1022,7 +1026,8 @@
cmd |= PCI_COMMAND_MASTER_ENABLE;
ltim = MIN (pb->def_ltim, pb->max_ltim);
}
- if (!(pd->enable)) {
+ if ((pd->enable &
+ (PCI_CONF_ENABLE_MEM|PCI_CONF_ENABLE_IO)) == 0) {
print_tag(pd->pc, pd->tag);
printf("Disabled due to lack of resources.\n");
cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
Index: sys/dev/pci/pciconf.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pciconf.h,v
retrieving revision 1.7
diff -u -r1.7 pciconf.h
--- sys/dev/pci/pciconf.h 28 Sep 2002 10:31:02 -0000 1.7
+++ sys/dev/pci/pciconf.h 25 Feb 2005 15:53:32 -0000
@@ -55,5 +55,7 @@
#define PCI_CONF_ENABLE_IO 0x08
#define PCI_CONF_ENABLE_MEM 0x10
#define PCI_CONF_ENABLE_BM 0x20
+#define PCI_CONF_ENABLE_PARITY 0x40
+#define PCI_CONF_ENABLE_SERR 0x80
-#define PCI_CONF_ALL 0x3f
+#define PCI_CONF_ALL 0xff
--- /dev/null 2005-02-26 00:48:30.000000000 +0900
+++ sys/arch/cobalt/cobalt/clockvar.h 2005-02-25 20:39:26.000000000 +0900
@@ -0,0 +1,30 @@
+/* $NetBSD: clockvar.h,v 1.1 2004/08/28 12:32:48 tsutsui Exp $ */
+/*
+ * Copyright (C) 2004 Izumi Tsutsui. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+extern void (*timer_start)(void *);
+extern long (*timer_read)(void *);
+extern void *timer_cookie;
--- /dev/null 2005-02-26 00:48:30.000000000 +0900
+++ sys/arch/cobalt/dev/gtreg.h 2005-02-25 20:39:33.000000000 +0900
@@ -0,0 +1,89 @@
+/* $NetBSD: gtreg.h,v 1.1 2004/08/28 12:32:48 tsutsui Exp $ */
+/*
+ * Copyright (c) 2003
+ * KIYOHARA Takashi. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#define GT_TIMER_COUNTER0 0x850
+#define GT_TIMER_COUNTER1 0x854
+#define GT_TIMER_COUNTER2 0x858
+#define GT_TIMER_COUNTER3 0x85c
+
+#define GT_TIMER_CTRL 0x864
+#define ENTC0 0x01
+#define TCSEL0 0x02
+#define ENTC1 0x04
+#define TCSEL1 0x08
+#define ENTC2 0x10
+#define TCSEL2 0x20
+#define ENTC3 0x40
+#define TCSEL3 0x80
+
+#define GT_PCI_COMMAND 0xc00
+#define PCI_BYTESWAP 0x00000001
+#define PCI_SYNCMODE 0x00000006
+#define PCI_PCLK_LOW 0x00000000
+#define PCI_PCLK_HIGH 0x00000002
+#define PCI_PCLK_SYNC 0x00000004
+
+#define GT_INTR_CAUSE 0xc18
+#define INTSUM 0x00000001
+#define MEMOUT 0x00000002
+#define DMAOUT 0x00000004
+#define MASTEROUT 0x00000008
+#define DMA0COMP 0x00000010
+#define DMA1COMP 0x00000020
+#define DMA2COMP 0x00000040
+#define DMA3COMP 0x00000080
+#define T0EXP 0x00000100
+#define T1EXP 0x00000200
+#define T2EXP 0x00000400
+#define T3EXP 0x00000800
+#define MASRDERR 0x00001000
+#define SLVWRERR 0x00002000
+#define MASWRERR 0x00004000
+#define SLVRDERR 0x00008000
+#define ADDRERR 0x00010000
+#define MEMERR 0x00020000
+#define MASABORT 0x00040000
+#define TARABORT 0x00080000
+#define RETRYCTR 0x00100000
+#define MASTER_INT0 0x00200000
+#define MASTER_INT1 0x00400000
+#define MASTER_INT2 0x00800000
+#define MASTER_INT3 0x01000000
+#define MASTER_INT4 0x02000000
+#define PCI_INT0 0x04000000
+#define PCI_INT1 0x08000000
+#define PCI_INT2 0x10000000
+#define PCI_INT3 0x20000000
+#define MASTER_INTSUM 0x40000000
+#define PCI_INTSUM 0x80000000
+
+#define GT_MASTER_MASK 0xc1c
+
+#define GT_PCI_MASK 0xc24
+
+#define GT_PCICFG_ADDR 0xcf8
+
+#define GT_PCICFG_DATA 0xcfc