Subject: Re: Does NetBSD 2.0 work with the Raq2?
To: None <port-cobalt@NetBSD.org>
From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
List: port-cobalt
Date: 01/08/2005 20:07:05
In article <Pine.NEB.4.61.0501061542550.7749@lain.ziaspace.com>
john@ziaspace.com wrote:
> Also, while I'm booting from the disk just fine, I still can't boot via
> NFS even with the 1.6.2 kernel. Any ideas, anyone?
Our bootloader only support boot from wd disks.
NFS boot still has kernel size restriction.
Adding kloader(4) support to cobalt might help, though.
> When I tried to load a full kernel with IP Filter, SCSI, ddb, ntp, and a
> bunch of other things, it got to where it says "Waiting 2 seconds for the
> SCSI bus...", then hung.
There is a problem PCI devices which use pci mem space.
Try attached patch, which includes patch in port-cobalt/27423.
(this patch is for -current, but it should be trivial to adapt it to 2.0)
Note we can't specify loading kernel file with
bootloader in 2.0 release while fixed were committed
after 2.0 is branched. (I've sent a pullup request yesterday)
I've put bootloader from my RaQ2 at:
http://www.ceres.dti.ne.jp/~tsutsui/netbsd/boot-cobalt-20040902.gz
---
Izumi Tsutsui
tsutsui@ceres.dti.ne.jp
---
Index: sys/dev/pci/pciconf.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pciconf.c,v
retrieving revision 1.23
diff -u -r1.23 pciconf.c
--- sys/dev/pci/pciconf.c 17 Mar 2004 20:27:57 -0000 1.23
+++ sys/dev/pci/pciconf.c 8 Jan 2005 10:53:18 -0000
@@ -705,10 +705,6 @@
PRIu64 " req)\n", pi->size);
return -1;
}
- if (!pb->io_32bit && pi->address > 0xFFFF) {
- pi->address = 0;
- pd->enable = 0;
- }
if (pd->ppb && pi->reg == 0) {
pd->ppb->ioext = extent_create("pciconf", pi->address,
pi->address + pi->size, M_DEVBUF, NULL, 0,
@@ -721,7 +717,12 @@
}
continue;
}
- pd->enable |= PCI_CONF_ENABLE_IO;
+ if (!pb->io_32bit && pi->address > 0xFFFF) {
+ pi->address = 0;
+ pd->enable &= ~PCI_CONF_ENABLE_IO;
+ } else {
+ pd->enable |= PCI_CONF_ENABLE_IO;
+ }
if (pci_conf_debug) {
print_tag(pd->pc, pd->tag);
printf("Putting %" PRIu64 " I/O bytes @ %#" PRIx64
@@ -775,7 +776,7 @@
if (pm->prefetch && !pb->pmem_64bit &&
pm->address > 0xFFFFFFFFULL) {
pm->address = 0;
- pd->enable = 0;
+ pd->enable &= ~PCI_CONF_ENABLE_MEM;
} else {
pd->enable |= PCI_CONF_ENABLE_MEM;
}
@@ -1005,7 +1006,10 @@
class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG);
misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG);
cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
- cmd |= PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE;
+ if (pd->enable & PCI_CONF_ENABLE_PARITY)
+ cmd |= PCI_COMMAND_PARITY_ENABLE;
+ if (pd->enable & PCI_CONF_ENABLE_SERR)
+ cmd |= PCI_COMMAND_SERR_ENABLE;
if (pb->fast_b2b)
cmd |= PCI_COMMAND_BACKTOBACK_ENABLE;
if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
@@ -1022,7 +1026,8 @@
cmd |= PCI_COMMAND_MASTER_ENABLE;
ltim = MIN (pb->def_ltim, pb->max_ltim);
}
- if (!(pd->enable)) {
+ if ((pd->enable &
+ (PCI_CONF_ENABLE_MEM|PCI_CONF_ENABLE_IO)) == 0) {
print_tag(pd->pc, pd->tag);
printf("Disabled due to lack of resources.\n");
cmd &= ~(PCI_COMMAND_MASTER_ENABLE |
Index: sys/dev/pci/pciconf.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pciconf.h,v
retrieving revision 1.7
diff -u -r1.7 pciconf.h
--- sys/dev/pci/pciconf.h 28 Sep 2002 10:31:02 -0000 1.7
+++ sys/dev/pci/pciconf.h 8 Jan 2005 10:53:18 -0000
@@ -55,5 +55,7 @@
#define PCI_CONF_ENABLE_IO 0x08
#define PCI_CONF_ENABLE_MEM 0x10
#define PCI_CONF_ENABLE_BM 0x20
+#define PCI_CONF_ENABLE_PARITY 0x40
+#define PCI_CONF_ENABLE_SERR 0x80
-#define PCI_CONF_ALL 0x3f
+#define PCI_CONF_ALL 0xff
Index: sys/arch/cobalt/dev/gt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/dev/gt.c,v
retrieving revision 1.12
diff -u -r1.12 gt.c
--- sys/arch/cobalt/dev/gt.c 30 Aug 2004 15:05:16 -0000 1.12
+++ sys/arch/cobalt/dev/gt.c 8 Jan 2005 10:53:18 -0000
@@ -28,6 +28,9 @@
#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: gt.c,v 1.12 2004/08/30 15:05:16 drochner Exp $");
+#include "opt_pci.h"
+#include "pci.h"
+
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/ioctl.h>
@@ -42,18 +45,21 @@
#include <sys/syslog.h>
#include <sys/types.h>
#include <sys/device.h>
+#include <sys/malloc.h>
+#include <sys/extent.h>
#include <machine/autoconf.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <dev/pci/pcivar.h>
+#ifdef PCI_NETBSD_CONFIGURE
+#include <dev/pci/pciconf.h>
+#endif
#include <cobalt/cobalt/clockvar.h>
#include <cobalt/dev/gtreg.h>
-#include "pci.h"
-
struct gt_softc {
struct device sc_dev;
@@ -117,6 +123,13 @@
pc->pc_bst = sc->sc_bst;
pc->pc_bsh = sc->sc_bsh;
+#ifdef PCI_NETBSD_CONFIGURE
+ pc->pc_ioext = extent_create("pciio", 0x10100000, 0x11ffffff,
+ M_DEVBUF, NULL, 0, EX_NOWAIT);
+ pc->pc_memext = extent_create("pcimem", 0x12000000, 0x13ffffff,
+ M_DEVBUF, NULL, 0, EX_NOWAIT);
+ pci_configure_bus(pc, pc->pc_ioext, pc->pc_memext, NULL, 0, 0);
+#endif
pba.pba_dmat = &pci_bus_dma_tag;
pba.pba_dmat64 = NULL;
pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
Index: sys/arch/cobalt/include/pci_machdep.h
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/include/pci_machdep.h,v
retrieving revision 1.7
diff -u -r1.7 pci_machdep.h
--- sys/arch/cobalt/include/pci_machdep.h 28 Aug 2004 13:33:31 -0000 1.7
+++ sys/arch/cobalt/include/pci_machdep.h 8 Jan 2005 10:53:18 -0000
@@ -34,6 +34,7 @@
* Machine-specific definitions for PCI autoconfiguration.
*/
#define __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
+#define __HAVE_PCI_CONF_HOOK
/*
* Forward declarations.
@@ -57,6 +58,9 @@
struct cobalt_pci_chipset {
bus_space_tag_t pc_bst; /* bus space tag for PCICFG regs */
bus_space_handle_t pc_bsh; /* bus space handle for PCICFG regs */
+
+ struct extent *pc_memext; /* PCI memory extent */
+ struct extent *pc_ioext; /* PCI I/O extent */
};
/*
@@ -77,3 +81,6 @@
void *pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
int, int (*)(void *), void *);
void pci_intr_disestablish(pci_chipset_tag_t, void *);
+void pci_conf_interrupt(pci_chipset_tag_t, int, int, int, int,
+ int *);
+int pci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t);
Index: sys/arch/cobalt/pci/pci_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/pci/pci_machdep.c,v
retrieving revision 1.16
diff -u -r1.16 pci_machdep.c
--- sys/arch/cobalt/pci/pci_machdep.c 28 Aug 2004 13:33:31 -0000 1.16
+++ sys/arch/cobalt/pci/pci_machdep.c 8 Jan 2005 10:53:18 -0000
@@ -34,6 +34,7 @@
#include <sys/systm.h>
#include <sys/errno.h>
#include <sys/device.h>
+#include <sys/extent.h>
#define _COBALT_BUS_DMA_PRIVATE
#include <machine/bus.h>
@@ -42,6 +43,7 @@
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcidevs.h>
+#include <dev/pci/pciconf.h>
#include <cobalt/dev/gtreg.h>
@@ -224,3 +226,28 @@
cpu_intr_disestablish(cookie);
icu_intr_disestablish(cookie);
}
+
+void
+pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz,
+ int *iline)
+{
+
+ /* not yet... */
+}
+
+int
+pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
+{
+
+ /* Don't configure the bridge and PCI probe. */
+ if (PCI_VENDOR(id) == PCI_VENDOR_GALILEO &&
+ PCI_PRODUCT(id) == PCI_PRODUCT_GALILEO_GT64011)
+ return 0;
+
+ /* Don't configure device 9 */
+ if (dev == 9)
+ return 0;
+
+ return PCI_CONF_ALL & ~(PCI_CONF_MAP_ROM |
+ PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE);
+}
Index: sys/arch/cobalt/conf/GENERIC
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/conf/GENERIC,v
retrieving revision 1.64
diff -u -r1.64 GENERIC
--- sys/arch/cobalt/conf/GENERIC 24 Nov 2004 20:49:20 -0000 1.64
+++ sys/arch/cobalt/conf/GENERIC 8 Jan 2005 10:55:20 -0000
@@ -158,6 +158,8 @@
pchb* at pci? dev ? function ?
pcib* at pci? dev ? function ?
+options PCI_NETBSD_CONFIGURE
+
# Cryptographic Devices
# PCI cryptographic devices
---
Cobalt Microserver Diagnostics - 'We serve it, you surf it'
Built Tue May 25 15:58:41 PDT 1999
1.LCD Test................................PASS
2.Controller Test.........................PASS
5.Bank 0:.................................64M
6.Bank 1:.................................64M
7.Bank 2:.................................64M
8.Bank 3:.................................64M
9.Serial Test.............................PASS
10.PCI Expansion Slot....................**EMPTY**
12.IDE Test................................PASS
13.Ethernet Test...........................PASS
16.RTC Test................................PASS
BOOTLOADER ramcode: selected partition /dev/hda1
Decompressing done
Executing bootloader kernel...
Decompressing - done.
>> NetBSD/cobalt 2.0G Bootloader, Revision 0.1 [@0x80f00000]
>> (tsutsui@mirage, Thu Sep 2 01:01:48 JST 2004)
>> Memory: 262144 k
>> PROM boot string: root=/dev/hda1 ro
Boot [wd0a:netbsd]:
Loading: wd0a:netbsd
2113328+257976 [81280+70801]=0x268450
Starting at 0x80001000
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 2.99.11 (COLT) #115: Mon Dec 20 22:38:47 JST 2004
tsutsui@mirage:/usr/src/sys/arch/cobalt/compile/COLT
total memory = 256 MB
avail memory = 247 MB
mainbus0 (root)
com0 at mainbus0 addr 0x1c800000 level 3: st16650a, working fifo
com0: console
cpu0 at mainbus0: QED RM5200 CPU (0x28a0) Rev. 10.0 with built-in FPU Rev. 10.0
cpu0: 32KB/32B 2-way set-associative L1 Instruction cache, 48 TLB entries
cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache
panel0 at mainbus0 addr 0x1f000000
gt0 at mainbus0 addr 0x14000000
pci0 at gt0
pci0: i/o space, memory space enabled, rd/line, wr/inv ok
pchb0 at pci0 dev 0 function 0: Galileo GT-64111 System Controller, rev 1
tlp0 at pci0 dev 7 function 0: DECchip 21143 Ethernet, pass 4.1
tlp0: interrupting at level 1
tlp0: Ethernet address 00:10:e0:00:5e:95
lxtphy0 at tlp0 phy 1: LXT970 10/100 media interface, rev. 3
lxtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
siop0 at pci0 dev 8 function 0: Symbios Logic 53c860 (ultra scsi)
siop0: interrupting at irq 4
scsibus0 at siop0: 8 targets, 8 luns per target
pcib0 at pci0 dev 9 function 0
pcib0: VIA Technologies VT82C586 PCI-ISA Bridge, rev 37
viaide0 at pci0 dev 9 function 1
viaide0: VIA Technologies VT82C586 (Apollo VP) ATA33 controller
viaide0: bus-master DMA support present
viaide0: primary channel configured to compatibility mode
viaide0: primary channel interrupting at irq 14
atabus0 at viaide0 channel 0
viaide0: secondary channel configured to compatibility mode
viaide0: secondary channel interrupting at irq 15
atabus1 at viaide0 channel 1
VIA Technologies VT83C572 USB Controller (USB serial bus, revision 0x02) at pci0 dev 9 function 2 not configured
tlp1 at pci0 dev 12 function 0: DECchip 21143 Ethernet, pass 4.1
tlp1: interrupting at level 2
tlp1: Ethernet address 00:10:e0:00:5e:97
lxtphy1 at tlp1 phy 1: LXT970 10/100 media interface, rev. 3
lxtphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
scsibus0: waiting 2 seconds for devices to settle...
sd0 at scsibus0 target 3 lun 0: <nEC, DKU364-, 0512> disk fixed
sd0: 1006 MB, 3992 cyl, 5 head, 103 sec, 512 bytes/sect x 2061108 sectors
sd0: sync (100.00ns offset 8), 8-bit (10.000MB/s) transfers, tagged queueing
wd0 at atabus0 drive 0: <IBM-DTTA-351680>
wd0: drive supports 16-sector PIO transfers, LBA addressing
wd0: 16124 MB, 32760 cyl, 16 head, 63 sec, 512 bytes/sect x 33022080 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 2 (Ultra/33)
wd0(viaide0:0:0): using PIO mode 4, Ultra-DMA mode 2 (Ultra/33) (using DMA)
boot device: wd0
root on wd0a dumps on wd0b
root file system type: ffs
---