Subject: Re: hardclock(9) for cobalt
To: None <port-cobalt@netbsd.org>
From: KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
List: port-cobalt
Date: 08/11/2004 02:37:52
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From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
Date: Mon, 2 Aug 2004 00:41:09 +0900

> Maybe we should attach the timer as usual device and initialize
> it in the attachment, and functions which enable the timer that
> will be called from cpu_initclocks(9) should also be registered
> in the attachment (like mvme68k or news68k ;-).

How is it now?

  gttmr0 at mainbus0: 32bit-Wide Timer/Counter on GT-64111


hardclock(9) is not called before being able to initialize softclock_si
now. That is, I think that it becomes safe. ;-)



microtime(9) uses timer0.
Probably, it will be better to add microtime(9) here, if possible.

--
kiyohara

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Index: arch/cobalt/cobalt/clock.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/cobalt/clock.c,v
retrieving revision 1.7
diff -c -r1.7 clock.c
*** arch/cobalt/cobalt/clock.c	5 Jul 2004 07:28:45 -0000	1.7
--- arch/cobalt/cobalt/clock.c	10 Aug 2004 16:56:55 -0000
***************
*** 34,39 ****
--- 34,41 ----
  #include <sys/kernel.h>
  #include <sys/device.h>
  
+ #include <machine/autoconf.h>
+ 
  #include <dev/clock_subr.h>
  
  #include <dev/ic/mc146818reg.h>
***************
*** 46,51 ****
--- 48,55 ----
  void
  cpu_initclocks()
  {
+ 	/* start timer0 */
+ 	timer_enable();
  
  	return;
  }
Index: arch/cobalt/conf/files.cobalt
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/conf/files.cobalt,v
retrieving revision 1.19
diff -c -r1.19 files.cobalt
*** arch/cobalt/conf/files.cobalt	17 Oct 2003 18:20:10 -0000	1.19
--- arch/cobalt/conf/files.cobalt	10 Aug 2004 16:56:55 -0000
***************
*** 23,28 ****
--- 23,32 ----
  attach gt at mainbus
  file arch/cobalt/dev/gt.c		gt
  
+ device gttmr
+ attach gttmr at mainbus
+ file arch/cobalt/dev/gttmr.c		gttmr
+ 
  file arch/cobalt/cobalt/autoconf.c
  file arch/cobalt/cobalt/bus.c
  file arch/cobalt/cobalt/clock.c
Index: arch/cobalt/include/autoconf.h
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/include/autoconf.h,v
retrieving revision 1.2
diff -c -r1.2 autoconf.h
*** arch/cobalt/include/autoconf.h	5 May 2000 03:27:22 -0000	1.2
--- arch/cobalt/include/autoconf.h	10 Aug 2004 16:56:56 -0000
***************
*** 27,32 ****
--- 27,35 ----
  
  #include <machine/bus.h>
  
+ inline void timer_enable(void);
+ inline void timer_disable(void);
+ 
  struct mainbus_attach_args {
  	char		*ma_name;
  	unsigned long	ma_addr;
Index: GENERIC
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/conf/GENERIC,v
retrieving revision 1.61
diff -c -r1.61 GENERIC
*** GENERIC	15 Jul 2004 03:53:46 -0000	1.61
--- GENERIC	10 Aug 2004 17:24:55 -0000
***************
*** 151,156 ****
--- 151,157 ----
  panel0 		at mainbus? addr 0x1f000000
  
  gt0 		at mainbus? addr 0x14000000
+ gttmr0 		at mainbus?
  
  pci* 		at gt0
  pchb* 		at pci? dev ? function ?

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*** /sys/arch/cobalt/dev/gttmr.c.orig	Wed Aug 11 02:13:24 2004
--- /sys/arch/cobalt/dev/gttmr.c	Wed Aug 11 01:45:48 2004
***************
*** 0 ****
--- 1,91 ----
+ /*
+  * Copyright (c) 2003
+  *     KIYOHARA Takashi.  All rights reserved.
+  *
+  * Redistribution and use in source and binary forms, with or without
+  * modification, are permitted provided that the following conditions
+  * are met:
+  * 1. Redistributions of source code must retain the above copyright
+  *    notice, this list of conditions and the following disclaimer.
+  * 2. Redistributions in binary form must reproduce the above copyright
+  *    notice, this list of conditions and the following disclaimer in the
+  *    documentation and/or other materials provided with the distribution.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  */
+ 
+ #include <sys/param.h>
+ #include <sys/device.h>
+ #include <sys/errno.h>
+ #include <sys/systm.h>
+ 
+ #include <machine/autoconf.h>
+ 
+ 
+ #define TIMER_COUNT_0		0x14000850
+ #define TIMER_COUNT_CTRL	0x14000864
+ #define ENTC0	(1 << 0)
+ #define TCSEL0	(1 << 1)
+ 
+ #define INTR_CAUSE		0x14000c18
+ #define T0EXP   (1 << 8)
+ 
+ #define TIMER0_INIT_VALUE	500000
+ 
+ 
+ struct gttmr_softc {
+ 	struct device   sc_dev;
+ };
+ 
+ static int gttmr_match(struct device *, struct cfdata *, void *);
+ static void gttmr_attach(struct device *, struct device *, void *);
+ 
+ 
+ CFATTACH_DECL(gttmr, sizeof(struct gttmr_softc),
+ 	gttmr_match, gttmr_attach, NULL, NULL);
+ 
+ 
+ inline void
+ timer_enable()
+ {
+ 	*(u_int32_t *)MIPS_PHYS_TO_KSEG1(TIMER_COUNT_CTRL) |= ENTC0;
+ }
+ 
+ inline void
+ timer_disable()
+ {
+ 	*(u_int32_t *)MIPS_PHYS_TO_KSEG1(TIMER_COUNT_CTRL) &= ~ENTC0;
+ }
+ 
+ 
+ static int
+ gttmr_match(struct device *parent, struct cfdata *match, void *aux)
+ {
+ 	return (1);
+ }
+ 
+ static void
+ gttmr_attach(struct device *parent, struct device *self, void *aux)
+ {
+ 	printf(": 32bit-Wide Timer/Counter on GT-64111\n");
+ 
+ 	/*
+ 	 * timer0 is working at the time of BIOS. It might be got blocked
+ 	 * and timer interruption may already have generated it. A timer0
+ 	 * must be disabled and interruption must be cleared.
+ 	 */
+ 	timer_disable();
+ 	*(u_int32_t *)MIPS_PHYS_TO_KSEG1(INTR_CAUSE) &= ~T0EXP;
+ 
+ 	/* initialize timer0 */
+ 	*(u_int32_t *)MIPS_PHYS_TO_KSEG1(TIMER_COUNT_0) = TIMER0_INIT_VALUE;
+ }

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