Hi.

I'm starting to look at the PCI stuff on the bebox a bit, and have
some questions.  In src/sys/arch/bebox/include/bus.h, we find the
following:

========================================================================
/*
 * Values for the Be bus space tag, not to be used directly by MI code.
 */
#define BEBOX_BUS_SPACE_IO      0x80000000      /* i/o space */
#define BEBOX_BUS_SPACE_MEM     0xC0000000      /* mem space */

/*
 * Address conversion as seen from a PCI master.
 */
#define MPC105_DIRECT_MAPPED_SPACE      0x80000000
#define PHYS_TO_PCI_MEM(x)      ((x) | MPC105_DIRECT_MAPPED_SPACE)
#define PCI_MEM_TO_PHYS(x)      ((x) & ~MPC105_DIRECT_MAPPED_SPACE)
========================================================================

According to the MPC 105 user's manual, this kind of matches address
map "A" (with BEBOX_BUS_SPACE_IO corresponding to the lower I/O range).

		processor phys addr	PCI phys addr
ISA/PCI I/O	80000000 - 8000FFFF	I/O 00000000 - 0000FFFF
PCI I/O		81000000 - BF7FFFFF	I/O 01000000 - 3F7FFFFF
PCI MEM		C0000000 - FEFFFFFF	MEM 00000000 - 3EFFFFFF

So it looks to me like MPC105_DIRECT_MAPPED_SPACE should be 0xC0000000.
Also, it looks like the PHYS_TO_PCI_MEM(x) and PCI_MEM_TO_PHYS(x) macros
are reversed.  I think that section should look like:

========================================================================
/*
 * Address conversion as seen from a PCI master.
 */
#define MPC105_DIRECT_MAPPED_SPACE      0xC0000000
#define PCI_MEM_TO_PHYS(x)      ((x) | MPC105_DIRECT_MAPPED_SPACE)
#define PHYS_TO_PCI_MEM(x)      ((x) & ~MPC105_DIRECT_MAPPED_SPACE)
========================================================================

Am I missing something?  If so, what?  ;-)

Assuming that the above is true, I think the BARs on the PCI devices
should be programmed with I/O values between 0x01000000 and 0x0fffffff
and memory values between 0 and 0x0fffffff (since we only map 256M for
each via BAT1 and BAT2).

-allen

-- 
 Allen Briggs                     briggs@wasabisystems.com
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