On Sat, Sep 18, 1999 at 08:32:57AM -0700, Todd Whitesel wrote:
> 
> I have started on a generic version of pci_tseng.c and friends, but the
> card still isn't displaying anything and I am beginning to suspect that
> it is because I can't find a good description of how the card's 16 meg
> PCI address space is laid out.
> 
> The atari code is full of mempory mapping and hardcoded numbers, and is
> very confusing to read. So far my best guess is that the VGA IO shows up
> at 0003c0-0003df or thereabouts, and the text screen shows up at 0a0000.
> This would all be inside the 16 meg region specified by PCI configuration
> register 0x10 for the card.

Huh?

I know this isa bit confusing, but VGA devices (especially older ones) take
a special role in PCI in that they may have registers, memory etc. outside
their PCI-configured areas - in fact, some older PCI VGA cards may even lack
all base registers in configuration space and map all their ressources to
the same, fixed addresses as their ISA predecessors did.

Looking at the S3 Trio in a Milan, you get the following situation:
 - PCI config space, as described in the PCI spec. This need not be memory
   mapped (it isn't in the Milan), but your lowlevel PCI routines should
   know how to get there.

 - IO space, at some offset in CPU memory space (where your PCI bridge puts
   it - $C0000000 in the Milan). A lot of VGA compatible registers may be at
   the usual ISA offsets (what is $3C0 in a PC becomes $3C0+IO_BASE, or
   $C00003C0 in the Milan). If the card allocates an IO range via a base
   register in the PCI config space, then there will be another
   (relocateable) set of IO registers starting at IO_BASE+<contents of base
   register>. These two are different register sets, and work different -
   the exakt workings are chip dependant, although some registers in the
   ISA-compatible range follow some common standard (the original IBM VGA).

 - Memory space, with an offset again depending on your PCI bridge. As
   above, the card may put memory in the standard ISA locations, ($A000:0 on
   a PC becomes MEMORY_BASE+$A0000). $A0000 is standard for low-res graphics
   modes, and $B0000/$B8000 for text modes IIRC.
   Again, if the card allocates a memory region via the PCI config space
   (most do), you get an additional memory region at MEMORY_BASE+<contents
   of base register>. The S3 Trio wants a 64MB memory window, where it maps
   different versions of the same RAM in different access modes. Again, you
   need docs for your chip to know what to do with that memory area.

Setting up the base registers is done by the PCI bios, so you don't know
where the exact memory and IO regions will be on the next boot - you have to
query the PCI bios or read the base registers. Most probable, PCI IO will be
above $400, and PCI memory will be above 16MB in systems that share PCI and
ISA address space (like most PCs and Milan, but not hades), and probably in
the other systems, too, since the PCI BIOS may *not* overlap resources
assigned via base registers with legacy-defined resources (ie. setting a
memory base to $A0000 is definitely wrong).

cu
Michael
-- 
Michael Schwingen, Ahornstrasse 36, 52074 Aachen