On 2 Jun 2001, John Fremlin wrote:

> Ben Harris <bjh21@netbsd.org> writes:
> > >OK I've written them (from the 710 T docs). I do hope that the abort
> > >fixups are no different, because I am disinclined to try to audit
> > >those ;-)
> >
> > You'll either need no fixups (base restored model), the same as ARM7 (late
> > (base updated model / late aborts) or the same as ARM6 (early aborts).
> > Check your data sheet.
>
> It doesn't give me a handy keyword. For data abt, ldr and str can
> apparently write back modified base registers, and ldm and stm insns
> can abort sort of halfway through. I guess this is the ARM6 early abt
> model?

Writing back modified base registers for LDR and STR is the "Base Updated
Abort Model", ie late aborts.  FWIW, I've just committed changes to make
the meanings of the fixup functions a little clearer.  There's some more
optimisation to be done there, in that early aborts are a subset of late
aborts, so they can share a lot of code.

> Bad news is that the port blows up eventually on an abort (with ARM 7
> fixups enabled) after (hopefully) jumping into main. It certainly gets
> to the very end of initarm, but then does nothing for several
> minutes. I don't know why it doesn't print the copyright . . . but
> once the world's most annoying panic came up - it disassembled an
> insn, didn't tell me where it was, then finished off a panicstr
> warning about being unable to fix things up with a \n.

What was the instruction?  The things that can't be fixed up seem to be:

LDR/STR in SVC mode with updated R13 base (ie stack over/underflow)
LDR/STR with updated R15 base (UNPREDICTABLE)
LDR/STR with Rn == Rm (UNPREDICTABLE)
LDR/STR with the shift specified by a register (UNPREDICTABLE)
LDR/STR with the address rotated (very silly)
LDM/STM with R15 as base register (UNPREDICTABLE)
LDC/STC in SVC mode with updated R13 base (ie stack over/underflow)
LDC/STC with updated R15 base (UNPREDICTABLE)

None of these should occur in real code, though you might plausibly get a
stack over/underflow.

> Index: disassem.c
> ===================================================================
> RCS file: /pub/NetBSD-CVS/syssrc/sys/arch/arm/arm/disassem.c,v
> retrieving revision 1.11
> diff -u -r1.11 disassem.c
> --- disassem.c  2001/03/04 04:15:58     1.11
> +++ disassem.c  2001/06/02 20:31:15
> @@ -279,7 +279,7 @@
>         matchp = 0;
>         insn = di->di_readword(loc);
>
> -/*     di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/
> +       di->di_printf("loc=%08x insn=%08x : ", loc, insn);
>
>         while (i_ptr->name) {
>                 if ((insn & i_ptr->mask) ==  i_ptr->pattern) {

That's not good.  It'll screw up other users of disassem() (like DDB).
The abort-fixup code should be printing the address itself.  I'll look at
making it do this.

-- 
Ben Harris                                                   <bjh21@netbsd.org>
Portmaster, NetBSD/arm26               <URL:http://www.netbsd.org/Ports/arm26/>