Thanks for the info.

The SA-1100 and IXP-1200 (the StrongArm core of the latter) both have the
same MMU instructions as eg SA-110 has. 

 The problem is that the hardware I know (SA-110 + 21285 co-processor has
it's RAM at address 0 and ROM somewhere else. This works only because the
21285 (aka footbridge) maps (they use the term alias in the specs) the ROM
to address 0 in the time-window after reset and the first memory write. That
window is enough to jump to the true ROM where the remainder of the
bootstrap happens.

 The IXP1200 does not (to my knowledge) perform that little trick, so my
concern is if NetBSD has any dependencies/requirements regarding the
physical
location of ROM and RAM (e.g. must RAM be at address 0). 

I am tempted to put ROM at address 0 and RAM somewhere else. The reset
vector would point at the ROM and the other vectors just re-direct to the
bottom of the physical RAM. If this will work, then the next question is
what configuration files need to be adjusted?
  
Regards,
Kurt Alstrup

-----Original Message-----
From: Chris Gilbert [mailto:chris@buzzbee.freeserve.co.uk]
Sent: Friday, October 06, 2000 5:10 PM
To: Alstrup, Kurt
Cc: port-arm32@netbsd.org
Subject: Re: Memory map guidelines


Hi,

On Fri, 06 Oct 2000, Alstrup, Kurt wrote:
> I am about to do an attempt to port the NetBSD OS to an IXP1200 processor,
> which contains an SA-1100 compatiple CPU core.

Does it have no MMU then?

[snip stuff I don't know about]

>  - The footbridge co-processor maps the ROM (a flash device on CATS) to
> address 0 until first write (to what I'm not sure) whereafter the SDRAM
> will be visible on address 0. The IXP1200 does not have that capability,
so
> can I put a ROM device at address 0 permanently and have the RAM at eg
> c000:0000 ?

Checking an arm ref book I have handy says that the 0 address contains an 
unconditional branch instruction to the relevant exeception handler, the 
exceptions and table look like:
Address		Exception vector
&00		Reset
&04		Undefined Instruction
&08		Software Interrupt
&0C		Abort (prefetch)
&10		Abort (data)
&14		Reserved
&18		IRQ
&1C		FIQ

You can probably find more details online from somewhere, or in the arm32 
code.  Hardest part maybe getting from the ROM exeception handlers into 
runtime RAM based ones.  But then perhaps you can cheat, and have in the rom

exception code a look up of an address in RAM, and check if it's 0 (but then

if the machine has just started up you don't know that the instruction will 
contain 0, but then if you can avoid doing any exceptions it might just work

;)

Cheers,
Chris