Bruce Martin wrote:
> 
> We are currently experiencing problems with two devices on our EBSA285-based
> board, running NetBSD/arm32. One device (i2c controller) is running at
> IPL_BIO, and another (Serial chip) is running at IPL_TTY. The serial chip
> runs fine under normal conditions, but when we use the i2c controller a lot,
> the Serial chip seems to battle to meet its interrupt timing requirements,
> and hangs up.
> 
> In NetBSD's footbridge irq scheme, are there actually 8 different priority
> levels, or are there actually less, with some IPL's actually sharing equal
> priorities?

From what we've seen, there are 8 levels.

> Will a higher IPL irq actually interrupt a lower IPL irq?

Yes. We've had major problems much like yours with a timing critical
interrupt in a device developed here. During the last week, however,
we've battled them down to two or three specific problems in NetBSD:

1. If an interrupt is asserted during the run of an interrupt with
higher IPL, it will be scheduled when the higher IPL irq returns. This
is good, since most high-IPL routines do their job quickly.

However, every time an interrupt returns, the soft interrupts are run
(dosoftints()). This no matter which IPL you came down from. This may
not be a bug but is bad nonetheless. They should only be run from the
lowest level of interrupt nesting.

2. The clock interrupt routine hardclock() runs soft interrupts directly
before returning. This gives about the same result as #1.

3. If two or more interrupts are asserted at the same time, only the
first will be chosen with regard to its IPL. The rest will be run in the
order they appear in the register.

If this doesn't seem like total bogus to you or others in the group, I
can post the changes.

/BR

-- 
Björn Roth, M.Sc                 bjorn.roth@softronic.se
Softronic Konsult AB             +46-(0)708-813146