>3) We have somehow messed with the virtual address (or had something else 
>at that virtual address which wasn't flushed out.  This is, I think, 
>possible, but improbable, especially if the problem is very repeatable.  
>However, this might explain why the code would work on an x86 with a 
>physically mapped cache, but not on a StrongARM where the cache is virtual.

The x86 cache is coherent wrt DMA in any case (in that all x86 cpus do bus 
snooping).  So the code will work on an x86 with no explicit cache flush at 
all.

p.