On Tue, 9 Nov 1999, Richard Earnshaw wrote:

> 
> davem@eastcoast.co.za said:
> > Then I checked out the "_bus_dmamap_sync(t, map, offset, len, ops)" in
> > "arm32/arm32/bus_dma.c" and noticed that nothing gets done for the
> > BUS_DMASYNC_POSTREAD and BUS_DMASYNC_POSTWRITE cases. 
> 
> There is of course, one blindingly obvious bug in this code, but I doubt 
> it will fix your particular problem...
> 
> since the write buffer is between the cache and the memory, not the cpu 
> and the cache; cache evictions are pushed to the write buffer.

Opps I'll fix that. I can confirm that this does not fix the described
problem with the fxp driver (I've dug out a card).

The POST* ops should not have to do anything.
The PRE* ops make sure that any cached data is written out to memory and
that the the cache is invalidated for the addresses in question. The
purgeD cache call does this. This ensures that for a write all data has
made it from the cache to main memory prior to the DMA and that the cache
does not have valid entries so that reads after the DMA will have to
refetch from main memory. Thus the POST* ops are no-ops (unless as Richard
points out you have bounce buffers etc. which we only use on ISA).
Actually going through the sync code again for the POST* ops should do
nothing and there should not be any relevant addresses in the cache.



Cheers,
				Mark