BTW, irrespective of whatever's broken in the cache flushing, it may
be beneficial to change the PLT format to avoid needing the I cache
flush.  There are two reasons for this:

1) The I cache flushes are a performance hit -- especially for
   functions that are called infrequently or only once.

2) The current PLT format is not thread-safe; if one thread enters a
   PLT slot while another has it half-updated, it will jump to the
   wrong place.

What I'd suggest is the following:

For bound entries, make the `address' field be the offset from the PLT
slot to the function, rather than a literal address.  This way the old
two-instruction code in the PLT slot will perform the function call
correctly, and no I cache flush is necessary.

If another thread tries to use the PLT slot while this is in progress,
it will simply load the old address and end up in the dynamic linker.

This would mean that all function calls through the PLT incur an extra
instruction penalty, but this is offset by the fact that we don't have
to call into the kernel any more to do the cache flush.

If we agree that this is a good idea, I'll do it.


[Of course it's obviously important for I cache flushing to work
correctly for other reasons (setting breakpoints, dynamically creating
code, etc.).  This is really a side issue, and should not detract from
fixing the real bug here.]