Charles M. Hannum wrote:
> 
> So the `warbling' is definitely due to an interrupt latency problem.

Real killer with IRQ/FIQ latency is, all interrupts are disabled during
entire cache invalidations and context switches (which typically take a
long time and are slow). FYI doing an entire cache invalidation for the
16KB Dcache involves reading 16KB of data to guarantee the 16KB in there
is actually thrown out :-)

When I tried enabling interrupts in these functions (which one _should_
be able to), the machine fell over running lmbench (which it shouldn't).
I don't know what the issue with this is, it demands more investigation
which Mark was going to do as he's better at these things (I might look
again today too).

Fixing this will cut interrupt latencies _massively_.

	Neil

-- 
Neil A. Carson