> The problem comes when there's an LDM instruction on the end of a page
> and the next page is not mapped. Can't remember if something also has to
> be happening with the write buffer, or if there has to be writeback on a
> register, or not. But that's basically it, anyway. When these in this
> certain condition are happening, it means that an oft unrecoverable
> fault will be taken during the instruction, which shouldn't happen.
> Certainly with the Revision S StrongARMs this has been ironed out, but I
> know it's there in the Rev J and Rev K silicon (look at the label on the
> chip---on my Shark the chip says SA110-S in the middle). Sometimes this
> will result in a binary banging out, and sometimes it will result in the
> machine just slowing down a lot whilst it faults and faults and faults.
> 
> Workarounds: As you can see, there aren't really any. One way would be
> to assemble the instruction twice and NOP one of them out. Another way
> would be to patch the binary afterwards (Pete Burwood wrote something to
> do this) but very occasionally this would not be possible to do. The
> best thing now I guess it to shuffle the LDMs around in the binary and
> get lucky which is what's happened everywhere so far :-)

The LDM instruction is not really necessary. It can be replaced with
multiple single load instructions. So, change gcc to do that,
recompile NetBSD, and release it. Let there be a flag so
people have the option of choosing. What do you say?

Kim0