Amit Gupta wrote:
> 
> Any chance of a RiscBSD related Wakefield show report, for those of us who
> sadly couldn't make it?

Ok, here's a brief list of what I saw :-

Shared libs, working, will be released with gcc 2.8 which is due out in
a month or so.
Digital NC's, running Java nicely, booting off one of the RPC.
Floating point library was there I think but I forgot to check.
New ethernet drivers, including an ANT one (can't remember which, I've
not taken much interest in that part)

Mark was actually working on a new IDE driver for either ICS or Simtecs
card (can't remember which)
Mark mentioned an optimized div routine in the works :)

I think there are other things, but due to contractual obligations they
can't release the code until they've got a signed bit of paper from the
company they're doing it for.

I think a mention of pmap was made, and is being paid for by a company,
so again, it's if they let it be released.

Big thing to note is that any code submitted to mark for putting in the
source needs to clearly state the copyright holder(s)  This is for legal
reasons and so that it's clear who did what :)

What this means for RiscBSD:
Shared libs will appear with the gcc 2.8
Source code for the Digital NC's will be appearing some time soon.
Digital want the source code to be available mainly so that developers
have access to one central place for source code for the NC :)

Other things will come along once the legal bits of paper are signed.

I hope this answers some fo the Riscbsd questions.

A few other things mentioned/shown at wakefield :
A7000+  it's a revamped A7000 with 48Mhz 7500FE chip, this means
hardware floating point, the A7000+ feels like a RPC 700, it's floating
point though is twice the speed of the SA.
Acorns NC was there running NCOS, which is basically Risc-OS 3.6 with
some bits added and some taken away, acorn showed their frames browser,
which means nested windows for Risc-OS.

Also seen was the prototype Acorn portable, looked good, but had no
local storage at the time.

The RPC 2 was mentioned as a multi-processor system due for release in
about a year, expected to have 5x SA 300MHz max for processors, giving
an estimated 1000+ MIPS.  A prototype is likely to be seen at AW 97.

I can't think of much else, if I do I'll post something.

Chris