Hello Mark,

in message <Pine.SGI.3.91.970103200105.6145P-100000@physig4.ph.kcl.ac.uk>
          Mark Brinicombe <amb@physig.ph.kcl.ac.uk> wrote:

> Oh this is very interesting ...
> This would explain exactly the behaviour I was seeing. This perhaps 

Yep.

> Q: why has this only recently started to be a problem.

OK I also have rev2 and still an ARM610 and RO 3.5.
I'm not sure if the revision indicates if the chip is broken or not.
Maybe ART haven't thought carefully and removed the special treatment of the
broken revision from RO 3.7.

> My SMC data sheet does not describe any bugs in the chips. I'll try and
> get all the note on revisions from SMC.

I don't know if they're actively informing about the problems.
Why should they be different than Intel was or Cyrix/IBM is nowadays (their
5x86 or 6x86 has a problem with cache updates which makes the machine crash
every now and then). :-(

> Anyway this bug certain fits with the behaviour I have observed so 
> hopefully my fix is actually the correct way to handle this.

I think, the c't says the same.
As you can easily imagine, there are some funny ways how you have to work
around this problem in DOS/Windows.

So long, MB