>I seem to remember that the last time this did the rounds we came to the
>conclusion that the globally most sensible answer was probably to introduce a
>work-a-around as part of a second level cache.

Yep what you need to a very fast way for cleaning the cache so what you want is
32K of addresses somewhere in the physical memory map that can be read as
fast as the SA can handle. The data would not actually matter. This would have
to be on the cpu card in order to do it faster than the normal bus speed.

The conclusion was that you need a new cpu card to do it.

You could share this function with a second level cache but you do not
really want to waste entries in the second level cache for the clean so
you would want extra logic so that you have another set of high speed addresses
(say at cache speed) that do not actually cause cache lookups.

In practice I expect we will have to wait for the successor to the SA-110 and
see if DEC/ARM improve things.

Cheers,
				Mark


-- 
Mark Brinicombe				amb@physig.ph.kcl.ac.uk
Research Associate			http://www.ph.kcl.ac.uk/~amb/
Department of Physics			tel: 0171 873 2894
King's College London			fax: 0171 873 2716