>I think it's up to ARM/DEC to come up with a decent cache flushing mechanism
>for the StrongARM.
>After all, this beast isn't only used in small embedded applications, but also
>for running operating systems in the RiscPC, the NetSurfer and the Newton which
>all suffer from this problem.

I seem to remember that the last time this did the rounds we came to the
conclusion that the globally most sensible answer was probably to introduce a
work-a-around as part of a second level cache. Makes sense as you're only going
to want a second level cache on systems where it is likely to be an issue. (and
conversely you are likely to want a second level cache on these sorts of systems
if you can afford it :).

Manar