Subject: Re: StrongARM
To: None <port-arm32@NetBSD.ORG>
From: Mark Brinicombe <amb@physig4.ph.kcl.ac.uk>
List: port-arm32
Date: 10/07/1996 18:23:03
Hi,
>I am sorry to ask this as I am sure it about to become a FAQ.
>
>What parts of RiscBSD work with the StrongARM / RiscOS 3.7 ?
>
>I have both as from last Saturday - and version 1.1 doesn't work (as I
>was told on this list).
>
>Is it a case of grab 1.2 now or wait a little?

All user code should work with the StrongARM fine. I have not found anything
yet in the 1.2 release that does not. Any user code that self modifies will
have problems but since binaries have read only text areas normally that is not
a concern.

As to the kernel.

A StrongARM kernel is required. This is not supported by generic kernels.

There are several reasons for this.

1. The abort behaviour is different
2. The cache behaviour is different
3. The tlb behaviour is different

Eventually it could be possible to merge SA support into a generic kernel but
at the moment you require a kernel built with a CPU_SA110 option. Also
you need the source code to go with this and I am still working on that.

You got your StrongARM earlier than me but support is coming along nicely.

Please note, StrongARM support is a tad more complex than it is for RiscOS
programs and possible RiscOS itself. The SA data sheet itself points out that
full context switching with the SA is much more complex than on earlier
processors.
Also a harvard architecure working with virtual addresses is a pig. Having a
virtual cache before was annoying in terms of the frequency of cache flushes
but now having a spilt data and instruction cache makes things more complex.
The
there is the fact that there is no simple hardware cache clean but needs to be
donw in software.
Oh forgot to meantion the write buffer that I also need to remember to drain
before tlb flushes etc....

Anyway, the current state is that I have a StrongARM kernel that works fine as
long as you do not enable the data cache. (i.e. it works with write buffer and
icache).
With the data cache enabled, I can boot the kernel but things start hanging
with context switches start. I hope that it will only be a day or so before I
have that fixed.

Cheers,
				Mark

-- 
Mark Brinicombe				amb@physig.ph.kcl.ac.uk
Research Associate			http://www.ph.kcl.ac.uk/~amb/
Department of Physics			tel: 0171 873 2894
King's College London			fax: 0171 873 2716