Re: Recent HEAD aarch64 images panic on Pi 2 / Pi 3

[Jared McNeill <jmcneill%invisible.ca@localhost>]

Hi John.

I think I've found the problem. Can you try the attached patch?

Take care,
Jared


On Fri, 26 Feb 2021, John Klos wrote:

> Hi,
>
> > I think I just fixed this one. Can you update and try again?
>
> I tried again from my own tree, and got the same results. I waited a day or 
> two, then tried your image with no changes at all, and got the same results.
>
> I wish I knew enough to help :(
>
> Thanks very much!
> John
? arm/pic/.pic_splfuncs.c.swp
Index: aarch64/include/locore.h
===================================================================
RCS file: /cvsroot/src/sys/arch/aarch64/include/locore.h,v
retrieving revision 1.8
diff -u -p -r1.8 locore.h
--- aarch64/include/locore.h	20 Feb 2021 19:27:35 -0000	1.8
+++ aarch64/include/locore.h	28 Feb 2021 11:35:00 -0000
@@ -58,11 +58,14 @@
 #define cpsie(psw)		daif_enable((psw))
 #define cpsid(psw)		daif_disable((psw))
 
+#define	INTR_ENABLE_MASK	(DAIF_I|DAIF_F)
 
-#define ENABLE_INTERRUPT()	\
-	reg_daifclr_write((DAIF_I|DAIF_F) >> DAIF_SETCLR_SHIFT)
-#define DISABLE_INTERRUPT()	\
-	reg_daifset_write((DAIF_I|DAIF_F) >> DAIF_SETCLR_SHIFT)
+#define ENABLE_INTERRUPT()						\
+	reg_daifclr_write(INTR_ENABLE_MASK >> DAIF_SETCLR_SHIFT)
+#define DISABLE_INTERRUPT()						\
+	reg_daifset_write(INTR_ENABLE_MASK >> DAIF_SETCLR_SHIFT)
+#define DISABLE_INTERRUPT_SAVE()					\
+	daif_disable(INTR_ENABLE_MASK)
 
 #define DAIF_MASK		(DAIF_D|DAIF_A|DAIF_I|DAIF_F)
 
Index: arm/include/cpufunc.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/include/cpufunc.h,v
retrieving revision 1.87
diff -u -p -r1.87 cpufunc.h
--- arm/include/cpufunc.h	7 Feb 2021 21:15:40 -0000	1.87
+++ arm/include/cpufunc.h	28 Feb 2021 11:35:00 -0000
@@ -353,8 +353,9 @@ enable_interrupts(uint32_t mask)
 #define restore_interrupts(old_cpsr)					\
 	(__set_cpsr_c((I32_bit | F32_bit), (old_cpsr) & (I32_bit | F32_bit)))
 
-#define	ENABLE_INTERRUPT()	cpsie(I32_bit)
-#define	DISABLE_INTERRUPT()	cpsid(I32_bit)
+#define	ENABLE_INTERRUPT()		cpsie(I32_bit)
+#define	DISABLE_INTERRUPT()		cpsid(I32_bit)
+#define	DISABLE_INTERRUPT_SAVE()	cpsid(I32_bit)
 
 static inline void cpsie(register_t psw) __attribute__((__unused__));
 static inline register_t cpsid(register_t psw) __attribute__((__unused__));
Index: arm/pic/pic_splfuncs.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/pic/pic_splfuncs.c,v
retrieving revision 1.18
diff -u -p -r1.18 pic_splfuncs.c
--- arm/pic/pic_splfuncs.c	22 Feb 2021 21:16:25 -0000	1.18
+++ arm/pic/pic_splfuncs.c	28 Feb 2021 11:35:00 -0000
@@ -75,12 +75,13 @@ _spllower(int newipl)
 	const int oldipl = ci->ci_cpl;
 	KDASSERT(panicstr || newipl <= ci->ci_cpl);
 	if (newipl < ci->ci_cpl) {
-		register_t psw = cpsid(I32_bit);
+		register_t psw = DISABLE_INTERRUPT_SAVE();
 		ci->ci_intr_depth++;
 		pic_do_pending_ints(psw, newipl, NULL);
 		ci->ci_intr_depth--;
-		if ((psw & I32_bit) == 0 || newipl == IPL_NONE)
-			cpsie(I32_bit);
+		if ((psw & I32_bit) == 0 || newipl == IPL_NONE) {
+			ENABLE_INTERRUPT();
+		}
 		cpu_dosoftints();
 	}
 	return oldipl;
@@ -113,7 +114,7 @@ splx(int savedipl)
 static void __noinline
 splx_dopendingints(struct cpu_info *ci, const int savedipl)
 {
-	const register_t psw = cpsid(I32_bit);
+	const register_t psw = DISABLE_INTERRUPT_SAVE();
 	ci->ci_intr_depth++;
 	while ((ci->ci_pending_ipls & ~__BIT(savedipl)) > __BIT(savedipl)) {
 		KASSERT(ci->ci_pending_ipls < __BIT(NIPL));
@@ -131,7 +132,7 @@ splx_dopendingints(struct cpu_info *ci, 
 	}
 	ci->ci_intr_depth--;
 	if ((psw & I32_bit) == 0) {
-		cpsie(I32_bit);
+		ENABLE_INTERRUPT();
 	}
 }
 #endif