Re: earmv4 binaries on RPI3 won't work?

[Izumi Tsutsui <tsutsui%ceres.dti.ne.jp@localhost>]

thorpej@ wrote:

> > SWP and SWPB instructions have been deperecated on ARMv6 and
> > removed since ARMv7 (because atomic LDREX and STREX insns are added).
> 
> We should probably emulate them.  It would be pretty simple using ufetch and ucas.

Should we have a PR for it so that someone[TM] will handle it? :-)

gdb on RPI0 shows the following trace for fsck_ffs.core on RPI3:

---
# gdb /sbin/fsck_ffs fsck_ffs.core 
GNU gdb (GDB) 7.12
Copyright (C) 2016 Free Software Foundation, Inc.
 [..snip..]
Core was generated by `fsck_ffs'.
Program terminated with signal SIGILL, Illegal instruction.
#0  0x7093dfac in ?? () from /lib/libc.so.12
(gdb) bt
#0  0x7093dfac in ?? () from /lib/libc.so.12
#1  0x70912290 in atomic_inc_ulong_nv () from /lib/libc.so.12
#2  0x70a46cac in prop_object_retain () from /lib/libprop.so.1
#3  0x70a48f90 in prop_dictionary_set () from /lib/libprop.so.1
#4  0x70a492a8 in ?? () from /lib/libprop.so.1
#5  0x70a46658 in _prop_object_internalize_by_tag () from /lib/libprop.so.1
#6  0x70a4706c in _prop_generic_internalize () from /lib/libprop.so.1
#7  0x70a438b0 in ?? () from /lib/libprop.so.1
#8  0x70a43ba4 in prop_dictionary_recv_ioctl () from /lib/libprop.so.1
#9  0x04cf97d8 in getdiskinfo ()
#10 0x04cf4a30 in setup ()
#11 0x04ceb2a4 in checkfilesys.constprop ()
#12 0x04cfe008 in main ()
(gdb) 
---

src/common/lib/libc/atomic/atomic_inc_32_nv_cas.c says:
> atomic_op_alias(atomic_inc_ulong_nv,_atomic_inc_32_nv)

atomic_inc_32_nv():

---
00000000 <_atomic_inc_32_nv>:
   0:   e1a0c00d        mov     ip, sp
   4:   e92dd8f0        push    {r4, r5, r6, r7, fp, ip, lr, pc}
   8:   e1a06000        mov     r6, r0
   c:   e24cb004        sub     fp, ip, #4
  10:   e5964000        ldr     r4, [r6]
  14:   e1a00006        mov     r0, r6
  18:   e2845001        add     r5, r4, #1
  1c:   e1a02005        mov     r2, r5
  20:   e1a01004        mov     r1, r4
  24:   ebfffffe        bl      0 <_atomic_cas_32>
  28:   e1540000        cmp     r4, r0
  2c:   1afffff7        bne     10 <_atomic_inc_32_nv+0x10>
  30:   e1a00005        mov     r0, r5
  34:   e89da8f0        ldm     sp, {r4, r5, r6, r7, fp, sp, pc}
---

atomic_cas_mp() (real function of _atomic_cas_32()):
---
000000c8 <_atomic_cas_mp>:
  c8:   e92d4030        push    {r4, r5, lr}
  cc:   e3a0e001        mov     lr, #1
  d0:   e59f3048        ldr     r3, [pc, #72]   ; 120 <_atomic_cas_mp+0x58>
  d4:   e1a0c1a0        lsr     ip, r0, #3
  d8:   e08f3003        add     r3, pc, r3
  dc:   e20cc07f        and     ip, ip, #127    ; 0x7f
  e0:   e083310c        add     r3, r3, ip, lsl #2

  e4:   e103409e        swp     r4, lr, [r3]
  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  e8:   ea000001        b       f4 <_atomic_cas_mp+0x2c>
  ec:   e3550000        cmp     r5, #0
  f0:   1afffffb        bne     e4 <_atomic_cas_mp+0x1c>
  f4:   e3540000        cmp     r4, #0
  f8:   1afffff9        bne     e4 <_atomic_cas_mp+0x1c>
  fc:   e590e000        ldr     lr, [r0]
 100:   e59f301c        ldr     r3, [pc, #28]   ; 124 <_atomic_cas_mp+0x5c>
 104:   e15e0001        cmp     lr, r1
 108:   05802000        streq   r2, [r0]
 10c:   e3a02000        mov     r2, #0
 110:   e08f3003        add     r3, pc, r3
 114:   e1a0000e        mov     r0, lr
 118:   e783210c        str     r2, [r3, ip, lsl #2]
 11c:   e8bd8030        pop     {r4, r5, pc}
 120:   00000040        .word   0x00000040
 124:   0000000c        .word   0x0000000c
---

So the swp insn in the atomic_cas functions causes the SIGILL on ARMv7.

---
Izumi Tsustui