Cortex-A9 boot problems with d-cache on Zynq

[Lloyd Parkes <lloyd%must-have-coffee.gen.nz@localhost>]

Hi,
A while back I figured I would try booting NetBSD on my ZYBO now that Zynq support is in the tree. My goal was get the NetBSD banner display, and I failed.

I found VERBOSE_INIT_ARM and after turning it on I could see that the boot was failing in arm_cpuinit at step “I”. Great. TLBs. It’s been 30 years since I did anything with page tables and even then I only read about them on my operating systems class.

After I managed to get the Xilinx SDK debugger running well enough to help me, I could see that the temporary L1 page table was being being setup correctly by arm_boot_l1pt_init, but by the time the TLBs were being invalidated in arm_cpuinit, the L1 page table contained garbage. Usually the same garbage it had before arm_boot_l1pt_init was run. 

I have no idea what’s going wrong. I threw in a whole pile of DSB instructions before and after the page table was constructed, but the only thing that worked was to turn off CPU_CONTROL_DC_ENABLE in SCTLR after calling cortex_init and before calling arm_boot_l1pt_init. 

So, why is this affecting me and (apparently) nobody else? I’m using a fairly new u-boot that I found on the internet. It even knows about NetBSD format u-boot images (although I was booting netbsd.bin). Given how much “fun” the page table technical reference was, I’m not looking forward digging in to the cache management stuff.

Cheers,
Lloyd