Re: fix for mirabox(armada370)

[Radoslaw Kujawa <radoslaw.kujawa%c0ff33.net@localhost>]

Hi.

> 
>> Is cpufunc_asm_pj4b.S really needed.  I've patched it to use 
>> cpufuncs_armv7 and the mirabox runs fine.  If the pb4b is
>> really armv7, then asm_pj4b is just redundant.
> 
> Yes, at least current code base.

Agreed about that, PJ4B is supposed to be ARMv7 compliant. 

The thing is that Armada support was written before ARMv7 support was finalised in NetBSD. If I remember correctly Armada support was developed on NetSBD 6.0 stable release. Then it was updated by me to 6.99 around March 2013, because Semihalf (original developers of this code) wanted to bring the port into our CVS tree. I still wasn't sure how much PJ4B differed from ARMv7, so I just left the cpufunc_asm_pj4b.S as it was written by them (after adjusting it a bit to compile on current code).

> PJ4B has customized L2 cache that supports DMA between the
> chache and integrated devices in SoC. The cache is controlled
> by memory mapped registers, isn't by coprosessor operations.
> I think there should be L2 cache management code in
> cpufunc_asm_pj4b.S...
> 
> I don't yet understand that L2 cache management is
> really needed or isn't. If L2 cache coherency is
> guaranteed by SoC, cpufunc_asm_pj4b.S is just redundant.

There's an AURORA_IO_CACHE_COHERENCY kernel option that is supposed to enable I/O cache coherency but it never worked for me, after I updated the port to NetBSD current.

I know it worked for the original developers of the code on 6.0 kernel, but after I updated it to NetBSD-current, it stopped working and I didn't dig deep enough to understand what has caused it not to work.

I'm sure zbb@ would know more about that, if he could be bothered to read the list :P.

-- 
Best regards,
Radoslaw Kujawa