Re: earmv6hf IEEE754 underflow problem

[Matt Thomas <matt%3am-software.com@localhost>]

> On Feb 24, 2015, at 4:23 PM, Tobias Nygren <tnn%NetBSD.org@localhost> wrote:
> 
> On Tue, 24 Feb 2015 20:49:49 +0000
> Richard Earnshaw <Richard.Earnshaw%buzzard.freeserve.co.uk@localhost> wrote:
> 
>>> ... but the userland does not have any of the fenv(3) stuff so
>>> I suppose it's still missing some code. Maybe this would be a good
>>> google SoC project?
> 
> Never mind this, it was a PEBCAK.
> 
>> 
>> You might also want to check
>> 
>> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0301h/Babfbcac.html
> 
> So, naively I tried to do ...
> 
> int fpscr;
> asm volatile(
>    "vmrs %[reg],FPSCR \r\n"
>    "bic %[reg],%[reg],#0x1000000\r\n"
>    "vmsr FPSCR,%[reg]\r\n"
>    "vmrs %[reg],FPSCR \r\n"
>    :[reg] "=r" (fpscr) : :
> );
> printf("FPSCR = %08x\n",fpscr);
> 
> ... thinking it would disable the Flush-to-zero bit.
> But the FPSCR register seems to be stuck at 0x3000000.
> Maybe I'm not allowed to write to it.

The armv6 vfp needs exception code to do denormals properly and that code has not been written.  Until that code is written, flush to zero is enforced.