Re: SHEEVAPLUG cache options

[Robert Swindells <rjs%fdy2.co.uk@localhost>]

Martin Husemann wrote:
>what is the state of L2 cache support for SHEEVAPLUG/Kirkwood?
>
>The config file refer to MV_L2_CACHE_ENABLE/MV_L2_CACHE_WRITE_THROUGH
>and MV_CACHE_RANGE_OPS, but the code tests for SHEEVA_L2_CACHE and
>SHEEVA_L2_CACHE_WT - and the commit mentions the latter being untested.

I haven't tried enabling it for a long time, the main way that things
used to break was when using the mvgbe controler.

I have the following diff that prints whether it is enabled or not.

Robert Swindells

diff -u -r1.105 cpu.c
--- cpu.c       1 Sep 2014 13:43:31 -0000       1.105
+++ cpu.c       17 Oct 2014 14:27:27 -0000
@@ -724,6 +724,15 @@
                print_cache_info(dv, &arm_scache, 1);
        }
 
+#ifdef CPU_SHEEVA
+       if (cputype == CPU_ID_MV88SV131) {
+               uint32_t l2cfg;
+
+               __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r"(l2cfg));
+               aprint_normal_dev(dv, "L2 cache %s\n",
+                               (l2cfg & (1u << 22)) ? "enabled" : "disabled");
+       }
+#endif
 
        switch (cpu_class) {
 #ifdef CPU_ARM2