Re: cubietruck boot panic

To: Robert Swindells <rjs%fdy2.co.uk@localhost>
Subject: Re: cubietruck boot panic
From: Matt Thomas <matt%3am-software.com@localhost>
Date: Sat, 28 Jun 2014 19:57:10 -0700
On Jun 28, 2014, at 2:23 PM, Robert Swindells <rjs%fdy2.co.uk@localhost> wrote:

> 
> Matt Thomas wrote:
>> On Jun 28, 2014, at 10:59 AM, Robert Swindells <rjs%fdy2.co.uk@localhost> 
>> wrote:
>> 
>>> 
>>> Matt Thomas wrote:
>>>> On Jun 28, 2014, at 10:34 AM, Robert Swindells <rjs%fdy2.co.uk@localhost> 
>>>> wrote:
>>>> 
>>>>> 
>>>>> Martin Husemann wrote:
>>>>>> On Sat, Jun 07, 2014 at 04:43:16PM +0100, Robert Swindells wrote:
>>>>>>> 
>>>>>>> I'm getting a panic in arm32_kernel_vm_init() on a cubietruck with a
>>>>>>> current kernel loaded using u-boot.
>>>>>> 
>>>>>> FWIW, a big endian kernel of -current as of a few hours ago and no 
>>>>>> verbose
>>>>>> arm init just worked fine for me.
>>>>> 
>>>>> It still panics in the same place for me without verbose init arm or
>>>>> built big endian.
>>>>> 
>>>>> How are you loading it ?
>>>>> 
>>>>> The panic looks correct to me. My reading of the source is that this
>>>>> is due to __HAVE_MM_MD_DIRECT_MAPPED_PHYS being defined, it doesn't
>>>>> compile without this though.
>>>> 
>>>> That's fine.  There's code to deal with that.
>>> 
>>> So why doesn't it work ?
>> 
>> Sure it's a cubie truck and not a cubie baord 2? 
> 
> Yes, it is a cubietruck, it has 2GB of RAM.
> 
> The panic is from when the kernel is being mapped and it has done all
> the 1M sections and is switching to smaller chunks for what is left.
> Should it be doing this if all RAM is already mapped ?
> 
> I'm building with tools from 5 June, do I need the binutils changes
> you made a couple of days ago ?

Nope, they wouldn't affect the kernel. 

Is __HAVE_MM_MD_DIRECT_MAPPED_PHYS enabled or disabled?  Is this a stock kernel?

U-Boot SPL 2014.01-09729-gd854c4d (Feb 23 2014 - 22:44:26)
Board: Cubietruck
DRAM: 2048 MiB
CPU: 960000000Hz, AXI/AHB/APB: 3/2/2
spl: not an uImage at 1600


U-Boot 2014.01-09729-gd854c4d (Feb 23 2014 - 22:44:26) Allwinner Technology

CPU:   Allwinner A20 (SUN7I)
Board: Cubietruck
I2C:   ready
DRAM:  2 GiB
WARNING: Caches not enabled
MMC:   SUNXI SD/MMC: 0
In:    serial
Out:   serial
Err:   serial
Net:   mii0
Hit any key to stop autoboot:  0 
sun7i# tftp ; bootm
Waiting for PHY auto negotiation to complete... done
ENET Speed is 1000 Mbps - FULL duplex connection
*** Warning: no boot file name; using 'C0A807BE.img'
Using mii0 device
TFTP from server 192.168.7.118; our IP address is 192.168.7.190
Filename 'C0A807BE.img'.
Load address: 0x50000000
Loading: #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #################################################################
         #
         1.3 MiB/s
done
Bytes transferred = 9546944 (91acc0 hex)
## Booting kernel from Legacy Image at 50000000 ...
   Image Name:   NetBSD/cubie 6.99.44
   Created:      2014-06-28  17:55:58 UTC
   Image Type:   ARM NetBSD Kernel Image (uncompressed)
   Data Size:    9546880 Bytes = 9.1 MiB
   Load Address: 80000000
   Entry Point:  80000000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
## Transferring control to NetBSD stage-2 loader (at address 80000000) ...
@DFG01H1IJKLMZMP<@BC-FG01H1IJKLM>
Early console started
CPU Speed is 960000000
Determining GPIO configuration
awin_bootstrap: cpu status: 0=0x1 1=0x3
awin_bootstrap: 2 cpus present
sdram_config = 0x30ed, memsize = 2048MB
arm32_bootmem_init: memstart=0x40000000, memsize=0x80000000, 
kernelstart=0x80000000
arm32_bootmem_init: kernelend=0x80944000
arm32_bootmem_init: adding 129886 free pages: [0x80944000..0xbfffffff] (VA 
0x80944000)
arm32_bootmem_init: adding 131072 free pages: [0x40000000..0x7fffffff] (VA 
0x80000000)
arm32_kernel_vm_init: changing pmap_directbase to 0x40000000
arm32_kernel_vm_init: 0 L2 pages are needed to map 0x980000 kernel bytes
arm32_kernel_vm_init: allocating page tables for kernel vmadd_pages: adding pv 
0x8091b388 (pa 0x80944000, va 0x80944000, 2 pages) at tail
add_pages: appending pv 0x8091b510 (0x80948000..0x80949fff) to 
0x80944000..0x80947fff
add_pages: appending pv 0x8091b524 (0x8094a000..0x8094bfff) to 
0x80944000..0x80949fff
add_pages: appending pv 0x8091b538 (0x8094c000..0x8094dfff) to 
0x80944000..0x8094bfff
add_pages: appending pv 0x8091b54c (0x8094e000..0x8094ffff) to 
0x80944000..0x8094dfff
add_pages: appending pv 0x8091b560 (0x80950000..0x80951fff) to 
0x80944000..0x8094ffff
add_pages: appending pv 0x8091b574 (0x80952000..0x80953fff) to 
0x80944000..0x80951fff
add_pages: appending pv 0x8091b588 (0x80954000..0x80955fff) to 
0x80944000..0x80953fff
add_pages: appending pv 0x8091b59c (0x80956000..0x80957fff) to 
0x80944000..0x80955fff
arm32_kernel_vm_init: allocating stacks
add_pages: appending pv 0x8091b854 (0x80958000..0x8095bfff) to 
0x80944000..0x80957fff
add_pages: appending pv 0x8091b840 (0x8095c000..0x8095ffff) to 
0x80944000..0x8095bfff
add_pages: appending pv 0x8091b82c (0x80960000..0x80963fff) to 
0x80944000..0x8095ffff
add_pages: appending pv 0x8091b818 (0x80964000..0x80967fff) to 
0x80944000..0x80963fff
add_pages: appending pv 0x8091b804 (0x80968000..0x8096bfff) to 
0x80944000..0x80967fff
add_pages: appending pv 0x8091b868 (0x8096c000..0x8096dfff) to 
0x80944000..0x8096bfff
add_pages: appending pv 0x8091b3c8 (0x8096e000..0x80971fff) to 
0x80944000..0x8096dfff
Creating L1 page table at 0x80944000
arm32_kernel_vm_init: adding L2 pt (VA 0x80948000, PA 0x80948000) for VA 
0xc0000000 (vm)
arm32_kernel_vm_init: adding L2 pt (VA 0x8094a000, PA 0x8094a000) for VA 
0xc0800000 (vm)
arm32_kernel_vm_init: adding L2 pt (VA 0x8094c000, PA 0x8094c000) for VA 
0xc1000000 (vm)
arm32_kernel_vm_init: adding L2 pt (VA 0x8094e000, PA 0x8094e000) for VA 
0xc1800000 (vm)
arm32_kernel_vm_init: adding L2 pt (VA 0x80950000, PA 0x80950000) for VA 
0xc2000000 (vm)
arm32_kernel_vm_init: adding L2 pt (VA 0x80952000, PA 0x80952000) for VA 
0xc2800000 (vm)
arm32_kernel_vm_init: adding L2 pt (VA 0x80954000, PA 0x80954000) for VA 
0xc3000000 (vm)
arm32_kernel_vm_init: adding L2 pt (VA 0x80956000, PA 0x80956000) for VA 
0xc3800000 (vm)
Mapping kernel
arm32_kernel_vm_init: adding chunk for kernel text 0x80000000..0x8041dfff (VA 
0x80000000)
add_pages: adding pv 0x8091b374 (pa 0x80000000, va 0x80000000, 527 pages) 
before pa 0x80944000
arm32_kernel_vm_init: adding chunk for kernel data/bss 0x8041e000..0x80943fff 
(VA 0x8041e000)
add_pages: appending pv 0x8091b3f0 (0x8041e000..0x80943fff) to 
0x80000000..0x8041dfff
add_pages: merging pv 0x8091b388 (0x80944000..0x80971fff) to 
0x80000000..0x80943fff
Listing Chunks
arm32_kernel_vm_init: pv 0x8091b374: chunk VA 0x80000000..0x80971fff (PA 
0x80000000, prot 3, cache 1)

Mapping Chunks
arm32_kernel_vm_init: mapping last chunk VA 0x40000000..0xbfffffff (PA 
0x40000000, prot 3, cache 1)
pmap_map_chunk: pa=0x40000000 va=0x40000000 size=0x80000000 resid=0x80000000 
prot=0x3 cache=1
sSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsSsS
devmap: 01c00000 -> 01efffff @ e4000000
pmap_map_chunk: pa=0x1c00000 va=0xe4000000 size=0x300000 resid=0x300000 
prot=0x3 cache=0
SSS
devmap: 00000000 -> 000fffff @ e4300000
pmap_map_chunk: pa=0x0 va=0xe4300000 size=0x100000 resid=0x100000 prot=0x3 
cache=1
S
                             Physical              Virtual        Num
                       Starting    Ending    Starting    Ending   Pages
               SDRAM: 0x40000000 0xbfffffff 0x40000000 0xbfffffff 262144
        text section: 0x80000000 0x8041dfff 0x80000000 0x8041dfff 527
        data section: 0x80420000 0x8091ac80 0x80420000 0x8091ac80 638
         bss section: 0x8091ac80 0x80942bf0 0x8091ac80 0x80942bf0 21
   L1 page directory: 0x80944000 0x80947fff 0x80944000 0x80947fff 2
   ABT stack (CPU 0): 0x80958000 0x80959fff 0x80958000 0x80959fff 1
   FIQ stack (CPU 0): 0x8095c000 0x8095dfff 0x8095c000 0x8095dfff 1
   IRQ stack (CPU 0): 0x80960000 0x80961fff 0x80960000 0x80961fff 1
   UND stack (CPU 0): 0x80964000 0x80965fff 0x80964000 0x80965fff 1
  IDLE stack (CPU 0): 0x80968000 0x80969fff 0x80968000 0x80969fff 1
           SVC stack: 0x8096c000 0x8096dfff 0x8096c000 0x8096dfff 1
      Message Buffer: 0x8096e000 0x80971fff 0x8096e000 0x80971fff 2
         Free Memory: 0x80972000 0xbfffffff                       129863
         Free Memory: 0x40000000 0x7fffffff                       131072
TTBR0=0x87ffc05b TTBR1=0x87ffc05b TTBCR=0x1 CONTEXTIDR=0
switching to new L1 page table @0x80944000... ttb (TTBCR=0x11 TTBR0=0x8094405b 
TTBR1=0x8094405b) hatchlingscpu_boot_secondary_processors: writing mbox with 0x2
 OK
nfreeblocks = 2, free_pages = 260935 (0x3fb47)
bootstrap done.
vectors vbar=0x802e9ca0 0x802e9ca0
init subsystems: stacks vectors undefined page pmap_physload pmap kpm tlb0 
kcpusets locks l1pt cache(l1pt) specials pools [ Kernel symbol table missing! ]
done.
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013, 2014
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 6.99.44 (CUBIETRUCK_INSTALL.MP)
total memory = 2048 MB
avail memory = 2018 MB
sysctl_createv: sysctl_create(machine_arch) returned 17
sysctl_createv: sysctl_locate(multicast) returned 2
sysctl_createv: sysctl_locate(multicast_kludge) returned 2
mainbus0 (root)
cpu0 at mainbus0 core 0: 960 MHz Cortex-A7 r0p4 (Cortex V7A core)
cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu0: 32KB/32B 2-way L1 VIPT Instruction cache
cpu0: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu0: 256KB/64B 8-way write-through L2 PIPT Unified cache
vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
cpu1 at mainbus0 core 1
armperiph0 at mainbus0
armgic0 at armperiph0: Generic Interrupt Controller, 160 sources (151 valid)
armgic0: 32 Priorities, 128 SPIs, 7 PPIs, 16 SGIs
armgtmr0 at armperiph0: ARMv7 Generic 64-bit Timer (24000 kHz)
armgtmr0: interrupting on irq 27
awinio0 at mainbus0
awingpio0 at awinio0
com0 at awinio0 port 0: ns16550a, working fifo
com0: console
awinwdt0 at awinio0: default period is 10 seconds
awinusb0 at awinio0 port 0
ohci0 at awinusb0: OHCI USB controller
ohci0: OHCI version 1.0
usb0 at ohci0: USB revision 1.0
ohci0: interrupting on irq 96
ehci0 at awinusb0: EHCI USB controller
ehci0: companion controller, 1 port each: ohci0
usb1 at ehci0: USB revision 2.0
ehci0: interrupting on irq 71
awinusb1 at awinio0 port 1
ohci1 at awinusb1: OHCI USB controller
ohci1: OHCI version 1.0
usb2 at ohci1: USB revision 1.0
ohci1: interrupting on irq 97
ehci1 at awinusb1: EHCI USB controller
ehci1: companion controller, 1 port each: ohci1
usb3 at ehci1: USB revision 2.0
ehci1: interrupting on irq 72
awinmmc0 at awinio0 port 0: SD/MMC interface
sdmmc0 at awinmmc0
ahcisata0 at awinio0: AHCI SATA controller
ahcisata0: interrupting on irq 88
ahcisata0: AHCI revision 1.10, 1 port, 32 slots, CAP 
0x6724ff80<CCCS,PSC,SSC,PMD,SAM,ISS=0x2=Gen2,SCLO,SAL,SALP,SSNTF,SNCQ>
atabus0 at ahcisata0 channel 0
awiniic0 at awinio0 port 0: Marvell TWSI controller
awiniic0: interrupting on irq 39
iic0 at awiniic0: I2C bus
awge0 at awinio0: Gigabit Ethernet Controller
gpio0 at awingpio0: 20 pins
gpio1 at awingpio0: 25 pins
gpio2 at awingpio0: 28 pins
gpio3 at awingpio0: 12 pins
gpio4 at awingpio0: 12 pins
gpio5 at awingpio0: 28 pins
gpio6 at awingpio0: 22 pins
cpu_boot_secondary_processors: writing mbox with 0x2
cpu_hatch(cpu1):  vectors vbar=0x802e9ca0 stacks tlbcpu1: 960 MHz Cortex-A7 
r0p4 (Cortex V7A core)
cpu1: DC enabled IC enabled WB disabled EABT branch prediction enabled
cpu1: 32KB/32B 2-way L1 VIPT Instruction cache
cpu1: 32KB/64B 4-way write-back-locking-C L1 PIPT Data cache
cpu1: 256KB/64B 8-way write-through L2 PIPT Unified cache
 vfpvfp1 at cpu1: NEON MPE (VFP 3.0+), rounding, NaN propagation, denormals
 interrupts md(0x800307f0) done!
uhub0 at usb0: Allwinner OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub1 at usb1: Allwinner EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
uhub2 at usb2: Allwinner OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub3 at usb3: Allwinner EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
ld0 at sdmmc0: <0x02:0x544d:SA08G:0x11:0x1f911406:0x0d9>
ld0: 7460 MB, 3789 cyl, 64 head, 63 sec, 512 bytes/sect x 15278080 sectors
ld0: 4-bit width, bus clock 50.000 MHz
boot device: <unknown>
root on md0a dumps on md0b
root file system type: ffs
WARNING: no TOD clock present
WARNING: using filesystem time
WARNING: CHECK AND RESET THE DATE!
erase ^?, werase ^W, kill ^U, intr ^C
Follow-Ups:
- Re: cubietruck boot panic
  - From: Robert Swindells
References:
- cubietruck boot panic
  - From: Robert Swindells
- Re: cubietruck boot panic
  - From: Martin Husemann
- Re: cubietruck boot panic
  - From: Robert Swindells
- Re: cubietruck boot panic
  - From: Matt Thomas
- Re: cubietruck boot panic
  - From: Robert Swindells
- Re: cubietruck boot panic
  - From: Matt Thomas
- Re: cubietruck boot panic
  - From: Robert Swindells
Prev by Date: Re: cubietruck boot panic
Next by Date: Re: cubietruck boot panic
Previous by Thread: Re: cubietruck boot panic
Next by Thread: Re: cubietruck boot panic
Indexes:
Home | Main Index | Thread Index | Old Index