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Re: TI AM35xx support
Here's a AM35xx patch for review. I created a new port out of Beagleboard
code. Most of peripherals and addresses are the same, but this one comes
with and Ethernet controller, which happens to be copied from an older
SoC (HAWK). Peripherals tested are currently: iic*, ld0, emac0 and gpio*.
Tested with CRANEBOARD, but should run on any other similar board.
$ uname -a
NetBSD crane 6.99.40 NetBSD 6.99.40 (CRANEBOARD) #12: Sun Apr 20 12:03:58 EEST
2014
pnu@wheezy:/home/pnu/src/netbsd_curr/src/sys/arch/evbarm/compile/obj/CRANEBOARD
evbarm
$ ifconfig emac0
emac0: flags=8843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST> mtu 1500
address: 4e:65:74:42:53:44
media: Ethernet autoselect (100baseTX full-duplex)
status: active
inet6 fe80::4c65:74ff:fe42:5344%emac0 prefixlen 64 scopeid 0x1
inet 192.168.1.66 netmask 0xff000000 broadcast 192.255.255.255
$ ping www.netbsd.org
PING www.netbsd.org (149.20.53.86): 64 data bytes
64 bytes from 149.20.53.86: icmp_seq=0 ttl=246 time=88.290385 ms
64 bytes from 149.20.53.86: icmp_seq=1 ttl=246 time=88.022039 ms
64 bytes from 149.20.53.86: icmp_seq=2 ttl=246 time=87.802847 ms
^C
----www.netbsd.org PING Statistics----
3 packets transmitted, 3 packets received, 0.0% packet loss
round-trip min/avg/max/stddev = 87.802847/88.038424/88.290385/0.244182 ms
diff --git a/am35xx_emacreg.h b/am35xx_emacreg.h
new file mode 100644
index 0000000..6bef434
--- /dev/null
+++ b/am35xx_emacreg.h
@@ -0,0 +1,84 @@
+/* $NetBSD: omapl1x_reg.h,v 1.1 2013/10/02 16:48:26 matt Exp $ */
+/*
+ * Copyright (c) 2013 Linu Cherian
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain this list of conditions
+ * and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce this list of conditions
+ * and the following disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
+ * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANY
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AM35XX_EMACREG_H
+#define _AM35XX_EMACREG_H
+
+/* EMAC */
+
+#define MAC_OFFSET 0x10000
+#define MACTXCONTROL (MAC_OFFSET + 0x4)
+#define MACTXTEARDOWN (MAC_OFFSET + 0x8)
+#define MACRXCONTROL (MAC_OFFSET + 0x14)
+#define MACRXTEARDOWN (MAC_OFFSET + 0x18)
+#define MACTXINTMASKSET (MAC_OFFSET + 0x88)
+#define MACTXINTMASKCLEAR (MAC_OFFSET + 0x8C)
+#define MACINVECTOR (MAC_OFFSET + 0x90)
+#define MACEOIVECTOR (MAC_OFFSET + 0x94)
+#define MACRXINTMASKSET (MAC_OFFSET + 0xA8)
+#define MACRXINTMASKCLEAR (MAC_OFFSET + 0xAC)
+#define MACINTMASKSET (MAC_OFFSET + 0xB8)
+#define MACRXMBPEN (MAC_OFFSET + 0x100)
+#define MACRXUNICASTSET (MAC_OFFSET + 0x104)
+#define MACRXUNICASTCLEAR (MAC_OFFSET + 0x108)
+#define MACRXMAXLEN (MAC_OFFSET + 0x10C)
+#define MACRXBUFOFFSET (MAC_OFFSET + 0x110)
+#define MACCONTROL (MAC_OFFSET + 0x160)
+#define MACSOFTRESET (MAC_OFFSET + 0x174)
+#define MACSRCADDRLO (MAC_OFFSET + 0x1D0)
+#define MACSRCADDRHI (MAC_OFFSET + 0x1D4)
+#define MACHASH1 (MAC_OFFSET + 0x1D8)
+#define MACHASH2 (MAC_OFFSET + 0x1DC)
+#define MACADDRLO (MAC_OFFSET + 0x500)
+#define MACADDRHI (MAC_OFFSET + 0x504)
+#define MACINDEX (MAC_OFFSET + 0x508)
+
+#define MAC_TX_HDP(p) (MAC_OFFSET + 0x600 + ((p) * 0x04))
+#define MAC_TX_CP(p) (MAC_OFFSET + 0x640 + ((p) * 0x04))
+
+#define MAC_RX_HDP(p) (MAC_OFFSET + 0x620 + ((p) * 0x04))
+#define MAC_RX_CP(p) (MAC_OFFSET + 0x660 + ((p) * 0x04))
+
+#define MAC_CR_OFFSET 0x0
+#define MAC_CR_SOFT_RESET (MAC_CR_OFFSET + 0x04)
+#define MAC_CR_INT_CONTROL (MAC_CR_OFFSET + 0x0c)
+#define MAC_CR_C_RX_THRESH_EN(p) (MAC_CR_OFFSET + (0x10 * (p)) + 0x10)
+#define MAC_CR_C_RX_EN(p) (MAC_CR_OFFSET + (0x10 * (p)) + 0x14)
+#define MAC_CR_C_TX_EN(p) (MAC_CR_OFFSET + (0x10 * (p)) + 0x18)
+#define MAC_CR_C_MISC_EN(p) (MAC_CR_OFFSET + (0x10 * (p)) + 0x1C)
+#define MAC_CR_C_RX_THRESH_STAT(p) (MAC_CR_OFFSET + (0x10 * (p)) + 0x40)
+#define MAC_CR_C_RX_STAT(p) (MAC_CR_OFFSET + (0x10 * (p)) + 0x44)
+#define MAC_CR_C_TX_STAT(p) (MAC_CR_OFFSET + (0x10 * (p)) + 0x48)
+#define MAC_CR_C_MISC_STAT(p) (MAC_CR_OFFSET + (0x10 * (p)) + 0x4C)
+
+#define MAC_MDIO_OFFSET 0x30000
+#define MACMDIOCONTROL (MAC_MDIO_OFFSET + 0x4)
+#define MACMDIOUSERACCESS0 (MAC_MDIO_OFFSET + 0x80)
+
+#define EMAC_CPPI_RAM_BASE 0x01E20000
+#define EMAC_CPPI_RAM_SIZE 0x2000
+
+#endif /*_AM35XX_EMACREG_H */
+
diff --git a/files.omap2 b/files.omap2
index f805eae..7909ff5 100644
--- a/files.omap2
+++ b/files.omap2
@@ -30,6 +30,7 @@ defflag opt_omap.h OMAP_5XXX: OMAP5
defflag opt_omap.h OMAP_5430: OMAP_5XXX
defflag opt_omap.h TI_AM335X: OMAP3
defflag opt_omap.h TI_DM37XX: OMAP3
+defflag opt_omap.h TI_AM35XX: OMAP3
# OBIO just an attach point
device obio { [addr=-1], [size=0], [intr=-1], [mult=1], [intrbase=-1],
[nobyteacc=0]
@@ -154,6 +155,11 @@ device cpsw: ether, ifnet, arp, mii, mii_phy
attach cpsw at obio
file arch/arm/omap/if_cpsw.c cpsw
+# EMAC Ethernet controller
+device emac: ether, ifnet, arp, mii, mii_phy
+attach emac at obio
+file arch/arm/omap/omapl1x_emac.c emac
+
device omapdma
attach omapdma at obio
file arch/arm/omap/omap3_sdma.c omapdma needs-flag
diff --git a/omap2_gpio.c b/omap2_gpio.c
index 3fc42cf..a0a439e 100644
--- a/omap2_gpio.c
+++ b/omap2_gpio.c
@@ -402,6 +402,16 @@ gpio_match(device_t parent, cfdata_t cfdata, void *aux)
return 1;
#endif
+#ifdef TI_AM35XX
+ if (oa->obio_addr == GPIO1_BASE_TI_AM35XX
+ || oa->obio_addr == GPIO2_BASE_TI_AM35XX
+ || oa->obio_addr == GPIO3_BASE_TI_AM35XX
+ || oa->obio_addr == GPIO4_BASE_TI_AM35XX
+ || oa->obio_addr == GPIO5_BASE_TI_AM35XX
+ || oa->obio_addr == GPIO6_BASE_TI_AM35XX)
+ return 1;
+#endif
+
return 0;
}
diff --git a/omap2_gpmcreg.h b/omap2_gpmcreg.h
index d539110..f20882c 100644
--- a/omap2_gpmcreg.h
+++ b/omap2_gpmcreg.h
@@ -56,6 +56,9 @@
#ifdef TI_DM37XX
#define GPMC_BASE 0x6e000000
#endif
+#ifdef TI_AM35XX
+#define GPMC_BASE 0x6e000000
+#endif
#define GPMC_REVISION 0x000
#define GPMC_SYSCONFIG 0x010
diff --git a/omap2_obio.c b/omap2_obio.c
index 6a8b285..029fdbc 100644
--- a/omap2_obio.c
+++ b/omap2_obio.c
@@ -184,6 +184,13 @@ obio_match(device_t parent, cfdata_t match, void *aux)
return 1;
#endif
+#ifdef OMAP2_OBIO_4_BASE
+ if (mb->mb_iobase == OMAP2_OBIO_4_BASE
+ && mb->mb_iosize == OMAP2_OBIO_4_SIZE
+ && (obio_attached & 16) == 0)
+ return 1;
+#endif
+
#ifdef TI_AM335X
if (obio_attached == 0)
return 1;
@@ -233,6 +240,10 @@ obio_attach(device_t parent, device_t self, void *aux)
else if (mb->mb_iobase == OMAP2_OBIO_3_BASE)
obio_attached |= 8;
#endif
+#ifdef OMAP2_OBIO_4_BASE
+ else if (mb->mb_iobase == OMAP2_OBIO_4_BASE)
+ obio_attached |= 16;
+#endif
#ifdef TI_AM335X
obio_attached = 1;
#endif
@@ -370,7 +381,7 @@ static const struct {
#if defined(OMAP_3430)
{ .name = "avic", .addr = INTC_BASE_3430, .required = true },
#endif
-#if defined(OMAP_3530)
+#if defined(OMAP_3530) || defined(TI_AM35XX)
{ .name = "avic", .addr = INTC_BASE_3530, .required = true },
#endif
{ .name = "gpio1", .addr = GPIO1_BASE, .required = false },
@@ -399,7 +410,7 @@ static const struct {
{ .name = "prcm", .addr = 0x44e00000, .required = true },
{ .name = "sitaracm", .addr = 0x44e10000, .required = true },
#endif
-#if defined(OMAP_3530)
+#if defined(OMAP_3530) || defined(TI_AM35XX)
{ .name = "omapdma", .addr = OMAP3530_SDMA_BASE, .required = true },
#endif
};
diff --git a/omap2_obioreg.h b/omap2_obioreg.h
index 54f4338..66c1565 100644
--- a/omap2_obioreg.h
+++ b/omap2_obioreg.h
@@ -178,4 +178,28 @@
#define GPIO6_BASE GPIO6_BASE_TI_DM37XX
#endif
+#if defined(TI_AM35XX)
+#define OMAP2_OBIO_0_BASE TI_AM35XX_L4_CORE_BASE
+#define OMAP2_OBIO_0_SIZE TI_AM35XX_L4_CORE_SIZE
+
+#define OMAP2_OBIO_1_BASE TI_AM35XX_L4_WAKEUP_BASE
+#define OMAP2_OBIO_1_SIZE TI_AM35XX_L4_WAKEUP_SIZE
+
+#define OMAP2_OBIO_2_BASE TI_AM35XX_L4_PERIPHERAL_BASE
+#define OMAP2_OBIO_2_SIZE TI_AM35XX_L4_PERIPHERAL_SIZE
+
+#define OMAP2_OBIO_3_BASE TI_AM35XX_L4_EMULATION_BASE
+#define OMAP2_OBIO_3_SIZE TI_AM35XX_L4_EMULATION_SIZE
+
+#define OMAP2_OBIO_4_BASE TI_AM35XX_L4_IPSS_BASE
+#define OMAP2_OBIO_4_SIZE TI_AM35XX_L4_IPSS_SIZE
+
+#define GPIO1_BASE GPIO1_BASE_TI_AM35XX
+#define GPIO2_BASE GPIO2_BASE_TI_AM35XX
+#define GPIO3_BASE GPIO3_BASE_TI_AM35XX
+#define GPIO4_BASE GPIO4_BASE_TI_AM35XX
+#define GPIO5_BASE GPIO5_BASE_TI_AM35XX
+#define GPIO6_BASE GPIO6_BASE_TI_AM35XX
+#endif
+
#endif /* _ARM_OMAP_OMAP2_OBIOREG_H_ */
diff --git a/omap2_reg.h b/omap2_reg.h
index 5133c9f..1450584 100644
--- a/omap2_reg.h
+++ b/omap2_reg.h
@@ -141,6 +141,23 @@
#define TI_DM37XX_L4_EMULATION_BASE 0x54000000
#define TI_DM37XX_L4_EMULATION_SIZE 0x00800000 /* 8MB */
+/* TI Sitara AM35xx (OMAP like) */
+
+#define TI_AM35XX_L4_CORE_BASE 0x48000000
+#define TI_AM35XX_L4_CORE_SIZE 0x01000000 /* 16MB */
+
+#define TI_AM35XX_L4_WAKEUP_BASE 0x48300000
+#define TI_AM35XX_L4_WAKEUP_SIZE 0x00040000 /* 256KB */
+
+#define TI_AM35XX_L4_PERIPHERAL_BASE 0x49000000
+#define TI_AM35XX_L4_PERIPHERAL_SIZE 0x00100000 /* 1MB */
+
+#define TI_AM35XX_L4_EMULATION_BASE 0x54000000
+#define TI_AM35XX_L4_EMULATION_SIZE 0x00800000 /* 8MB */
+
+#define TI_AM35XX_L4_IPSS_BASE 0x5C000000
+#define TI_AM35XX_L4_IPSS_SIZE 0x03000000 /* 48MB */
+
/*
* Clock Management registers base, offsets, and size
*/
@@ -168,6 +185,9 @@
#ifdef TI_DM37XX
#define OMAP2_CM_BASE 0x48004000
#endif
+#ifdef TI_AM35XX
+#define OMAP2_CM_BASE 0x48004000
+#endif
#define OMAP2_CM_CLKSEL_MPU 0x140
#define OMAP2_CM_FCLKEN1_CORE 0x200
@@ -427,6 +447,9 @@
#ifdef TI_DM37XX
#define OMAP2_PRM_BASE 0x48306000
#endif
+#ifdef TI_AM35XX
+#define OMAP2_PRM_BASE 0x48306000
+#endif
#define OMAP2_PRM_SIZE 0x00002000 /* 8k */
@@ -667,7 +690,7 @@
/*
* GPT - General Purpose Timers
*/
-#if defined(OMAP_3430) || defined(OMAP_3530) || defined(TI_DM37XX)
+#if defined(OMAP_3430) || defined(OMAP_3530) || defined(TI_DM37XX) ||
defined(TI_AM35XX)
#define GPT1_BASE 0x48318000
#define GPT2_BASE 0x49032000
#define GPT3_BASE 0x49034000
@@ -767,6 +790,13 @@
#define GPIO5_BASE_TI_DM37XX 0x49056000
#define GPIO6_BASE_TI_DM37XX 0x49058000
+#define GPIO1_BASE_TI_AM35XX 0x48310000
+#define GPIO2_BASE_TI_AM35XX 0x49050000
+#define GPIO3_BASE_TI_AM35XX 0x49052000
+#define GPIO4_BASE_TI_AM35XX 0x49054000
+#define GPIO5_BASE_TI_AM35XX 0x49056000
+#define GPIO6_BASE_TI_AM35XX 0x49058000
+
#define GPIO_IRQSTATUS1 0x018
#define GPIO_IRQENABLE1 0x01c
#define GPIO_WAKEUPENABLE 0x020
diff --git a/omap3_i2c.c b/omap3_i2c.c
index 719e1dd..d2af544 100644
--- a/omap3_i2c.c
+++ b/omap3_i2c.c
@@ -99,7 +99,7 @@ omap3_i2c_match(device_t parent, cfdata_t match, void *opaque)
{
struct obio_attach_args *obio = opaque;
-#if defined(OMAP_3430) || defined(OMAP_3530)
+#if defined(OMAP_3430) || defined(OMAP_3530) || defined(TI_AM35XX)
if (obio->obio_addr == I2C1_BASE_3530 ||
obio->obio_addr == I2C2_BASE_3530 ||
obio->obio_addr == I2C3_BASE_3530)
diff --git a/omap3_sdhc.c b/omap3_sdhc.c
index 23e89f3..5ec4487 100644
--- a/omap3_sdhc.c
+++ b/omap3_sdhc.c
@@ -101,7 +101,7 @@ CFATTACH_DECL_NEW(obiosdhc, sizeof(struct obiosdhc_softc),
static int
obiosdhc_match(device_t parent, cfdata_t cf, void *aux)
{
-#if defined(OMAP_3430) || defined(OMAP_3530) || defined(OMAP4)
+#if defined(OMAP_3430) || defined(OMAP_3530) || defined(OMAP4) ||
defined(TI_AM35XX)
struct obio_attach_args * const oa = aux;
#endif
#ifdef TI_AM335X
@@ -114,7 +114,7 @@ obiosdhc_match(device_t parent, cfdata_t cf, void *aux)
|| oa->obio_addr == SDMMC2_BASE_3430
|| oa->obio_addr == SDMMC3_BASE_3430)
return 1;
-#elif defined(OMAP_3530)
+#elif defined(OMAP_3530) || defined(TI_AM35XX)
if (oa->obio_addr == SDMMC1_BASE_3530
|| oa->obio_addr == SDMMC2_BASE_3530
|| oa->obio_addr == SDMMC3_BASE_3530)
@@ -166,7 +166,7 @@ obiosdhc_attach(device_t parent, device_t self, void *aux)
sc->sc.sc_flags |= SDHC_FLAG_WAIT_RESET;
sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
#endif
-#if defined(OMAP_3530)
+#if defined(OMAP_3530) || defined(TI_AM35XX)
sc->sc.sc_flags &= ~SDHC_FLAG_SINGLE_ONLY;
#endif
sc->sc.sc_host = sc->sc_hosts;
diff --git a/omapl1x_emac.c b/omapl1x_emac.c
index 354a2f0..b2dad30 100644
--- a/omapl1x_emac.c
+++ b/omapl1x_emac.c
@@ -32,8 +32,6 @@
__KERNEL_RCSID(0, "$NetBSD: omapl1x_emac.c,v 1.1 2013/10/02 16:48:26 matt Exp
$");
-#include "opt_omapl1x.h"
-
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/device.h>
@@ -54,8 +52,13 @@ __KERNEL_RCSID(0, "$NetBSD: omapl1x_emac.c,v 1.1 2013/10/02
16:48:26 matt Exp $"
#include <dev/mii/mii.h>
#include <dev/mii/miivar.h>
+#ifndef TI_AM35XX
#include <arm/omap/omapl1x_reg.h>
#include <arm/omap/omap_tipb.h>
+#else
+#include <arch/arm/omap/omap2_obiovar.h>
+#include <arch/arm/omap/am35xx_emacreg.h>
+#endif
struct emac_cppi_bd;
@@ -125,6 +128,10 @@ struct emac_softc {
struct emac_chain *rx_chain[EMAC_NRXDESCS];
struct emac_channel tx_chan;
struct emac_channel rx_chan;
+#ifdef TI_AM35XX
+ bus_space_handle_t sc_irqack;
+ u_int sc_irqack_offset;
+#endif
};
#define EMAC_INTROFF_RXTH 0
@@ -195,8 +202,10 @@ struct emac_softc {
#define USERACCESS_PHY(x) (((x) & 0x1f) << 16)
#define USERACCESS_DATA(x) ((x) & 0xffff)
+#ifndef TI_AM35XX
extern struct arm32_bus_dma_tag omapl1x_bus_dma_tag;
extern struct arm32_bus_dma_tag omapl1x_desc_dma_tag;
+#endif
#define EMAC_READ(sc, o) \
bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (o))
@@ -258,6 +267,17 @@ static void emac_mii_writereg(device_t dev, int phy, int
reg, int val);
CFATTACH_DECL_NEW(emac, sizeof(struct emac_softc),
emac_match, emac_attach, NULL, NULL);
+#ifdef TI_AM35XX
+static void
+am35xx_emac_lvl_intr_clear(struct emac_softc * const sc, uint8_t mask)
+{
+ /* Ack all EMAC interrupts at 0x48002594 */
+ bus_space_write_4(sc->sc_iot, sc->sc_irqack,
+ sc->sc_irqack_offset, mask);
+ bus_space_read_4(sc->sc_iot, sc->sc_irqack, sc->sc_irqack_offset);
+}
+#endif
+
static int
emac_mii_wait (struct emac_softc * const sc)
{
@@ -813,6 +833,7 @@ emac_soft_intr (void *arg)
if (__predict_false(mask & HOSTPEND)) {
device_printf(sc->sc_dev,
"Host Error. Stopping the device\n");
+ mutex_exit(sc->sc_hwlock);
emac_ifstop(ifp, 0);
return;
@@ -821,8 +842,6 @@ emac_soft_intr (void *arg)
emac_int_enable(sc);
mutex_exit(sc->sc_hwlock);
-
- return;
}
static int
@@ -836,6 +855,10 @@ emac_intr (void *arg)
softint_schedule(sc->sc_soft_ih);
+#ifdef TI_AM35XX
+ am35xx_emac_lvl_intr_clear(sc, 0x0f);
+#endif
+
return 1;
}
@@ -1191,7 +1214,15 @@ emac_desc_list_create (struct emac_cppi_bd **desc, void
*desc_base_ptr, int ndes
static int
emac_match (device_t parent, struct cfdata *match, void *aux)
{
+#ifndef TI_AM35XX
return 1;
+#else
+ struct obio_attach_args * const oa = aux;
+
+ if (oa->obio_addr == 0x5c000000 && oa->obio_size >= 0x4000)
+ return 1;
+#endif
+ return 0;
}
static void
@@ -1199,7 +1230,11 @@ emac_attach (device_t parent, device_t self, void *aux)
{
struct emac_softc * const sc = device_private(self);
struct ifnet * const ifp = &sc->sc_if;
+#ifndef TI_AM35XX
struct tipb_attach_args *tipb = aux;
+#else
+ struct obio_attach_args * const oa = aux;
+#endif
const char * const xname = device_xname(self);
prop_dictionary_t dict = device_properties(self);
struct emac_channel *tx_chan, *rx_chan;
@@ -1207,6 +1242,9 @@ emac_attach (device_t parent, device_t self, void *aux)
struct emac_chain *entry;
int i;
+ sc->sc_dev = self;
+
+#ifndef TI_AM35XX
sc->sc_iot = tipb->tipb_iot;
sc->sc_intr = tipb->tipb_intr;
sc->sc_addr = tipb->tipb_addr;
@@ -1215,6 +1253,22 @@ emac_attach (device_t parent, device_t self, void *aux)
/* descriptors to be allocated from cppi ram range */
sc->sc_desct = &omapl1x_desc_dma_tag;
sc->sc_buft = &omapl1x_bus_dma_tag;
+#else
+ sc->sc_iot = oa->obio_iot;
+ sc->sc_intr = oa->obio_intrbase;
+ sc->sc_addr = oa->obio_addr;
+ sc->sc_size = oa->obio_size;
+
+ sc->sc_desct = oa->obio_dmat;
+ sc->sc_buft = oa->obio_dmat;
+
+ if (bus_space_map(sc->sc_iot, 0x48002000, 0x1000, 0, &sc->sc_irqack))
+ panic("can't map registers\n");
+
+ sc->sc_irqack_offset = (0x270 + 0x324);
+ am35xx_emac_lvl_intr_clear(sc, 0x0f);
+#endif
if (bus_space_map(sc->sc_iot, sc->sc_addr, sc->sc_size, 0, &sc->sc_ioh))
panic("%s: Cannot map registers", device_xname(self));
@@ -1244,8 +1298,7 @@ emac_attach (device_t parent, device_t self, void *aux)
prop_data_t eaprop = prop_dictionary_get(dict, "mac-address");
if (eaprop == NULL) {
- device_printf(sc->sc_dev,
- "using fake station address\n");
+ device_printf(self, "using fake station address\n");
/* 'N' happens to have the Local bit set */
sc->sc_enaddr[0] = 'N';
sc->sc_enaddr[1] = 'e';
@@ -1260,8 +1313,6 @@ emac_attach (device_t parent, device_t self, void *aux)
ETHER_ADDR_LEN);
}
- sc->sc_dev = self;
-
/* First map the tx and rx descriptors */
if (emac_desc_map(sc, tx_chan, EMAC_TXDESCS_SIZE)) {
aprint_error_dev(self, "Can't map tx desc's\n");
@@ -1371,6 +1422,7 @@ emac_attach (device_t parent, device_t self, void *aux)
sc->sc_soft_ih = softint_establish(SOFTINT_NET, emac_soft_intr, sc);
/* Register all the emac interrupts */
+#ifndef TI_AM35XX
intr_establish(sc->sc_intr + EMAC_INTROFF_RXTH, IPL_VM, IST_LEVEL_HIGH,
emac_intr, sc);
intr_establish(sc->sc_intr + EMAC_INTROFF_RX, IPL_VM, IST_LEVEL_HIGH,
@@ -1379,6 +1431,16 @@ emac_attach (device_t parent, device_t self, void *aux)
emac_intr, sc);
intr_establish(sc->sc_intr + EMAC_INTROFF_MISC, IPL_VM, IST_LEVEL_HIGH,
emac_intr, sc);
+#else
+ intr_establish(sc->sc_intr + EMAC_INTROFF_RXTH, IPL_VM, IST_LEVEL,
+ emac_intr, sc);
+ intr_establish(sc->sc_intr + EMAC_INTROFF_RX, IPL_VM, IST_LEVEL,
+ emac_intr, sc);
+ intr_establish(sc->sc_intr + EMAC_INTROFF_TX, IPL_VM, IST_LEVEL,
+ emac_intr, sc);
+ intr_establish(sc->sc_intr + EMAC_INTROFF_MISC, IPL_VM, IST_LEVEL,
+ emac_intr, sc);
+#endif
if_attach(ifp);
ether_ifattach(ifp, sc->sc_enaddr);
@@ -1406,6 +1468,4 @@ fail:
bus_dmamem_free(sc->sc_desct, &tx_chan->desc_seg, tx_chan->desc_rseg);
bus_dmamem_free(sc->sc_desct, &rx_chan->desc_seg, rx_chan->desc_rseg);
-
- return;
}
--
-panu
Masanobu SAITOH writes:
> Hello, panu.
>
> (2013/01/12 17:41), panu.finnila%iki.fi@localhost wrote:
> > Hi Jeff,
> >
> > Thanks for the reply. I already tried, but it seems that AM35xx is
> > much closer to OMA3530 than AM335x. Can't boot BEAGLEBONE kernel
> > on AM35xx because every single peripheral register has different
> > address.
> >
> > Also the AM35xx Ethernet controller is different from one that is
> > used at AM33xx but I hope there are some similar registers.
> >
> > http://processors.wiki.ti.com/index.php/OMAP35x_to_AM35x_Hardware_Migration_Guide
> > http://processors.wiki.ti.com/index.php/AM35x_To_AM335x_Hardware_Migration_Guide
> >
> > --
> > -panu
> >
> > Jeff Rizzo writes:
> > > On 1/11/13 11:47 AM, panu.finnila%iki.fi@localhost wrote:
> > > > Hello all,
> > > >
> > > > Anyone tried NetBSD on TI AM35xx based board? I'm able to run current
> > > > BEAGLEBOARD kernel with 6.0 userland without any source changes.
> > > > It runs relatively well on SD card. It halts after couple of minutes
> > > > running idle but it's ok for now.
> > > >
> > > > But the Ethernet driver is missing... To enable Ethernet controller
> > > > it would need a new memory region (IPSS, 0x5C000000 - 0x5EFFFFFF) to
> > > > be added into the omap2_obio driver. Is this legal?
> > > >
> > > > # dmesg | grep ^obio
> > > > obio0 at mainbus0 base 0x48000000-0x48ffffff: On-Board IO
> > > > obio1 at mainbus0 base 0x48300000-0x4833ffff: On-Board IO
> > > > obio2 at mainbus0 base 0x49000000-0x490fffff: On-Board IO
> > > > obio3 at mainbus0 base 0x54000000-0x547fffff: On-Board IO
> > > > obio4 at mainbus0 base 0x5c000000-0x5effffff: On-Board IO
> > > >
> > > > I tweaked BEAGLEBONEs if_cpsw driver a little. Now it's able to
> > > > correctly read the MAC address without crashing, no more:
> > > >
> > > > cpsw0 at obio4 addr 0x5c000000-0x5c007fff intrbase 67: TI CPSW
> > Ethernet
> > > > cpsw0: Ethernet address 00:50:c2:1e:af:fa
> > > > cpsw0: no PHY found!
> > > >
> > > > # ifconfig cpsw0
> > > > cpsw0: flags=8802<BROADCAST,SIMPLEX,MULTICAST> mtu 1500
> > > > address: 00:50:c2:1e:af:fa
> > > > media: Ethernet manual (none)
> > > >
> > >
> > > The BEAGLEBONE kernel (in -current) works on, well, the BeagleBone,
> > > which has an AM355x in it. You might want to start there... It's
> > > missing a few things (USB), but is getting there.
> > >
> > > +j
>
> This problem might be fixed by today's commit by ozaki-r. Do you still have
> the board?
>
>
> > Module Name: src
> > Committed By: ozaki-r
> > Date: Wed Feb 26 03:58:33 UTC 2014
> >
> > Modified Files:
> > src/sys/arch/arm/omap: if_cpsw.c if_cpswreg.h
> >
> > Log Message:
> > Make cpsw driver work without uboot support
> >
> > On some eval boards such as BeagleBone, the cpsw device is initialized
> > rightly by the uboot of the boards so that the cpsw driver doesn't need
> > to do some initializations but works fine.
> >
> > The patch adds initializations to make the driver work solely. It also
> > adds support for 1000BaseT (RGMII) PHY that is equipped on some boards,
> > e.g., CKB-3352.
> >
> > Reviewed by christos@
> >
> >
> > To generate a diff of this commit:
> > cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/omap/if_cpsw.c
> > cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/omap/if_cpswreg.h
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