Re: ARMADAXP status

[KIYOHARA Takashi <kiyohara%kk.iij4u.or.jp@localhost>]

Hi! Matt,


From: KIYOHARA Takashi <kiyohara%kk.iij4u.or.jp@localhost>
Date: Sat, 22 Jun 2013 23:13:08 +0900 (JST)

> From: Matt Thomas <matt%3am-software.com@localhost>
> Date: Sat, 22 Jun 2013 02:45:49 -0700
> 
> > On Jun 22, 2013, at 2:13 AM, KIYOHARA Takashi 
> > <kiyohara%kk.iij4u.or.jp@localhost> wrote:
> > 
> > > OpenBlocks AX3
> > 
> > that's a nice box.  seems to be a bit expensive @ 60,000 yen.
> > 
> > Did you modify the config file to reduce memory to 1G since
> > it's hardcoded at 2GB in the ARMADAXP config file?
> 
> hmm,  I think, I modifed to 1GB...
> I try once more with 'csv update'.

Probably my modifier may have been last time ugly.  X-)
I try to more support to OpenBlocks AX3.

Thanks,
--
kiyohara


openblocks> bootm
## Booting kernel from Legacy Image at 02000000 ...
   Image Name:   NetBSD/armadaxp 6.99.21
   Created:      2013-06-25  10:32:45 UTC
   Image Type:   ARM NetBSD Kernel Image (uncompressed)
   Data Size:    3663360 Bytes =  3.5 MB
   Load Address: 00200000
   Entry Point:  00200000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK
## Transferring control to NetBSD stage-2 loader (at address 00200000) ...
[ Kernel symbol table missing! ]
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005,
    2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013
    The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
    The Regents of the University of California.  All rights reserved.

NetBSD 6.99.21 (ARMADAXP) #1: Tue Jun 25 19:31:43 JST 2013
       
lance%pride.sins.soum.co.jp@localhost:/usr/src/sys/arch/evbarm/compile/ARMADAXP
total memory = 1024 MB
avail memory = 1000 MB
mainbus0 (root)
cpu0 at mainbus0 core 0: Sheeva 88SV584x rev 2 (Marvell V core)
cpu0: DC enabled IC enabled WB enabled LABT branch prediction enabled
cpu0: 32KB/32B 4-way L1 Instruction cache
cpu0: 32KB/32B 8-way write-back-locking-C L1 Data cache
cpu0: 1024KB/32B 16-way write-through L2 Unified cache
mvsoc0 at mainbus0: Marvell MV78460 Rev. A0  Armada XP
mvsoc0: CPU Clock 1333.000 MHz  SysClock 667.000 MHz  TClock 250.000 MHz
mvsoctmr0 at mvsoc0 unit 0 offset 0x20300-0x203ff irq 37: Marvell SoC Timer
com0 at mvsoc0 unit 0 offset 0x12000-0x1201f irq 41: ns16550a, working fifo
com0: console
com1 at mvsoc0 unit 1 offset 0x12100-0x1211f irq 42: ns16550a, working fifo
com2 at mvsoc0 unit 2 offset 0x12200-0x1221f irq 43: ns16550a, working fifo
com3 at mvsoc0 unit 3 offset 0x12300-0x1231f irq 44: ns16550a, working fifo
mvsocrtc0 at mvsoc0 unit 0 offset 0x10300-0x10317 irq 50: Marvell SoC Real Time 
Clock
ehci0 at mvsoc0 unit 0 offset 0x50000-0x51fff irq 45: Marvell USB 2.0 Interface
usb0 at ehci0: USB revision 2.0
ehci1 at mvsoc0 unit 1 offset 0x51000-0x52fff irq 46: Marvell USB 2.0 Interface
usb1 at ehci1: USB revision 2.0
mvpex0 at mvsoc0 unit 0 offset 0x40000-0x41fff irq 58: Marvell PCI Express 
Interface
pci0 at mvpex0
vendor 0x11ab product 0x7846 (miscellaneous memory, revision 0x01) at pci0 dev 
0 function 0 not configured
mvpex1 at mvsoc0 unit 1 offset 0x44000-0x45fff irq 59: Marvell PCI Express 
Interface
pci1 at mvpex1
vendor 0x11ab product 0x7846 (miscellaneous memory, revision 0x01) at pci1 dev 
0 function 0 not configured
mvpex2 at mvsoc0 unit 2 offset 0x48000-0x49fff irq 60: Marvell PCI Express 
Interface
pci2 at mvpex2
mvpex3 at mvsoc0 unit 3 offset 0x4c000-0x4dfff irq 61: Marvell PCI Express 
Interface
pci3 at mvpex3
mvpex4 at mvsoc0 unit 4 offset 0x42000-0x43fff irq 99: Marvell PCI Express 
Interface
pci4 at mvpex4
mvpex5 at mvsoc0 unit 5 offset 0x82000-0x83fff irq 103: Marvell PCI Express 
Interface

<hungup...:->