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Re: marvell relation support 20100413

KIYOHARA Takashi wrote:
>I operate DiscoveryII on PegasosII(ofppc) by gt(sys/dev/marvell/gt.c).
>My PegasosII boots with NFS by my mvgbe.

I have not looked at your latest patch in detail yet but don't want to
hold up you committing it.

I have been working on adding Kirkwood support to your 20091017 patch,
the main changes in my tree look as if they will still apply to your
latest patch.

The changes are:

Remove the a4x bus space code and just use COM_REGMAP in com_mv.c.

Modify the mvsoc attachment code:

-device mvsoc { [unit = -1], [offset = -1], [irq = -1] } : bus_space_generic
-file   arch/arm/marvell/orion.c                mvsoc
-file   arch/arm/marvell/orion_intr.c
-file   arch/arm/marvell/orion_space.c
-file   arch/arm/marvell/orion_a4x_space.c
-file   arch/arm/marvell/orion_a4x_io.S
-file   arch/arm/marvell/orion_dma.c
+define  mvsoc { [unit = -1], [offset = -1], [irq = -1] } : bus_space_generic
+device  orion: mvsoc
+attach orion at mainbus
+file    arch/arm/marvell/orion.c                orion
+file    arch/arm/marvell/orion_intr.c           orion
+file    arch/arm/marvell/orion_space.c          orion
+device  kirkwood: mvsoc
+attach kirkwood at mainbus
+file    arch/arm/marvell/kirkwood.c             kirkwood
+file    arch/arm/marvell/kirkwood_intr.c        kirkwood
+file    arch/arm/marvell/kirkwood_space.c       kirkwood
+file    arch/arm/marvell/orion_dma.c            orion | kirkwood

The kernel configs now become:


# The main bus device
mainbus0 at root

# The boot cpu
cpu0    at mainbus?

# Marvell MV88Fxx81 Orion System-on-Chip
orion0  at mainbus?

# On-chip PCI Express Interface
mvpex0  at orion? offset 0x40000 irq 11
#mvpex1 at orion? offset 0x30000 irq 13 # 1182 and 1281 only

# On-chip PCI Interface
gtpci0  at orion? offset 0x30000 irq ?


# The main bus device
mainbus0 at root

# The boot cpu
cpu0    at mainbus?

# Marvell MV88F6xxx Kirkwood System-on-chip
kirkwood0 at mainbus?

# Interrupt Controller
#kirkwoodicu0 at kirkwood? offset 0x20000 irq ?

# On-chip PCI Express Interface
mvpex0 at kirkwood? offset 0x40000 irq 9

Robert Swindells

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