Subject: Re: L2 caches and cpufuncs.
To: Matt Thomas <>
From: Chris Gilbert <>
List: port-arm
Date: 09/13/2007 00:05:26
Matt Thomas wrote:
> The Freescale i.MX31 has a 128KB L2 cache controller.  It's not clear
> how it
> should interact with the normal cpu functions.
> Obviously, since the L2 looks like memory to the CPU, any icache ops don't
> even need to know the L2 exists.
> The question is should the dcache ops know about it?  There's only one
> component that really needs to know it's there, bus_dma.  So maybe there
> should be a separate interface for it to do L2 cache ops.

That would seem reasonable.  Although it would be nice if it was
compiled away on machines that don't need it, but then it would be nice
if other cpu_funcs eg cpwait did that as well.

> Comments?