The Freescale i.MX31 has a 128KB L2 cache controller.  It's not clear  
how it
should interact with the normal cpu functions.

Obviously, since the L2 looks like memory to the CPU, any icache ops  
don't
even need to know the L2 exists.

The question is should the dcache ops know about it?  There's only one
component that really needs to know it's there, bus_dma.  So maybe there
should be a separate interface for it to do L2 cache ops.

Comments?