Subject: Re: initialization probrem for GPIO of pxa2x0
To: None <bsh@netbsd.org, pooka@netbsd.org, nonaka@netbsd.org,>
From: KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
List: port-arm
Date: 08/08/2007 17:36:32
----Next_Part(Wed_Aug__8_17_36_32_2007_124)--
Content-Type: Text/Plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi! all,


From: KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
Date: Sat, 21 Jul 2007 03:05:55 +0900 (JST)

>             I will initialize GPIO in the substrate dependence part. 


> From: KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
> Date: Mon, 21 May 2007 23:55:44 +0900 (JST)
> 
> > Our GPIO initiation for each devices has a lot of problem.
> > 
> > First, PXA2{55,60,70} is different for the GPIO functions.  For instance,
> > AC97_SDATA_IN_1 is GPIO99 (PXA270) and GPIO32 (PXA2{55,60}).  Then,
> > pxa2x0_ac97.c initializes it excluding this pin. 
> > 
> > Next, for instance PXA2{55,60} has I2C bus controller.  However
> > pxa2x0_i2c.c sets function GPIO_ALT_FN_1_IN for GPIO11[78].  Moreover
> > PXA2{55,60} hasn't GPIO11[78].  It will go to panic() possibly.  X-<
> > 
> > 
> > I think we must set configure the GPIO in init_arm() and other.  And
> > test to GPIO configuration from DEVICE_match().  If enable a device
> > then to attach a device.
> > It just to the way of gxpcic_match.c::gxpcic_match(). 
> > 
> > 
> > Shall I correct them to other PXA2xx machines?


I attached this patch.
It is NOT test.  I tried to build only.  ;-)

If you need also initialize the GPIO of pcic then you can set
pxa2[57]x_pcic_gpioconf in BOARD_gpioconf[].  And you set board-dep
nPCE[12] in boarddep_gpioconf[].

# And, the support of PXA270 of gumstix will be started.  ;-)

Thanks,
--
kiyohara


----Next_Part(Wed_Aug__8_17_36_32_2007_124)--
Content-Type: Text/Plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename="pxa2x0_gpio.diff"

Index: arm/xscale/pxa2x0_ac97.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0_ac97.c,v
retrieving revision 1.5
diff -u -r1.5 pxa2x0_ac97.c
--- arm/xscale/pxa2x0_ac97.c	4 Mar 2007 05:59:38 -0000	1.5
+++ arm/xscale/pxa2x0_ac97.c	8 Aug 2007 07:47:03 -0000
@@ -53,6 +53,7 @@
 #include <dev/ic/ac97reg.h>
 #include <dev/ic/ac97var.h>
 
+#include <arm/xscale/pxa2x0cpu.h>
 #include <arm/xscale/pxa2x0reg.h>
 #include <arm/xscale/pxa2x0var.h>
 #include <arm/xscale/pxa2x0_gpio.h>
@@ -232,11 +233,23 @@
 pxaacu_match(struct device *parent, struct cfdata *cf, void *aux)
 {
 	struct pxaip_attach_args *pxa = aux;
+	struct pxa2x0_gpioconf *gpioconf;
+	u_int gpio;
+	int i;
 
 	if (pxa->pxa_addr != PXA2X0_AC97_BASE ||
 	    pxa->pxa_intr != PXA2X0_INT_AC97)
 		return (0);
 
+	gpioconf = CPU_IS_PXA250 ? pxa25x_pxaacu_gpioconf :
+	    pxa27x_pxaacu_gpioconf;
+	for (i = 0; gpioconf[i].pin != -1; i++) {
+		gpio = pxa2x0_gpio_get_function(gpioconf[i].pin);
+		if (GPIO_FN(gpio) != GPIO_FN(gpioconf[i].value) ||
+		    GPIO_FN_IS_OUT(gpio) != GPIO_FN_IS_OUT(gpioconf[i].value))
+			return (0);
+	}
+
 	pxa->pxa_size = PXA2X0_AC97_SIZE;
 
 	return (1);
@@ -267,11 +280,6 @@
 	/* Make sure the AC97 clock is enabled */
 	pxa2x0_clkman_config(CKEN_AC97, true);
 	delay(100);
-	pxa2x0_gpio_set_function(31, GPIO_CLR | GPIO_ALT_FN_2_OUT);
-	pxa2x0_gpio_set_function(30, GPIO_CLR | GPIO_ALT_FN_2_OUT);
-	pxa2x0_gpio_set_function(28, GPIO_CLR | GPIO_ALT_FN_1_IN);
-	pxa2x0_gpio_set_function(29, GPIO_CLR | GPIO_ALT_FN_1_IN);
-	delay(100);
 
 	/* Do a cold reset */
 	acu_reg_write(sc, AC97_GCR, 0);
Index: arm/xscale/pxa2x0_com.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0_com.c,v
retrieving revision 1.7
diff -u -r1.7 pxa2x0_com.c
--- arm/xscale/pxa2x0_com.c	10 Dec 2006 12:46:48 -0000	1.7
+++ arm/xscale/pxa2x0_com.c	8 Aug 2007 07:47:03 -0000
@@ -55,8 +55,10 @@
 #include <dev/ic/comreg.h>
 #include <dev/ic/comvar.h>
 
+#include <arm/xscale/pxa2x0cpu.h>
 #include <arm/xscale/pxa2x0reg.h>
 #include <arm/xscale/pxa2x0var.h>
+#include <arm/xscale/pxa2x0_gpio.h>
 
 #include "locators.h"
 
@@ -72,32 +74,48 @@
 	struct pxaip_attach_args *pxa = aux;
 	bus_space_tag_t bt = &pxa2x0_a4x_bs_tag;	/* XXX: This sucks */
 	bus_space_handle_t bh;
-	int rv;
+	struct pxa2x0_gpioconf *gpioconf;
+	u_int gpio;
+	int rv, i;
 
 	switch (pxa->pxa_addr) {
 	case PXA2X0_FFUART_BASE:
 		if (pxa->pxa_intr != PXA2X0_INT_FFUART)
 			return (0);
+		gpioconf = CPU_IS_PXA250 ? pxa25x_com_ffuart_gpioconf :
+			    pxa27x_com_ffuart_gpioconf;
 		break;
 
 	case PXA2X0_STUART_BASE:
 		if (pxa->pxa_intr != PXA2X0_INT_STUART)
 			return (0);
+		gpioconf = CPU_IS_PXA250 ? pxa25x_com_stuart_gpioconf :
+			    pxa27x_com_stuart_gpioconf;
 		break;
 
 	case PXA2X0_BTUART_BASE:	/* XXX: Config file option ... */
 		if (pxa->pxa_intr != PXA2X0_INT_BTUART)
 			return (0);
+		gpioconf = CPU_IS_PXA250 ? pxa25x_com_btuart_gpioconf :
+			    pxa27x_com_btuart_gpioconf;
 		break;
 
 	case PXA2X0_HWUART_BASE:
 		if (pxa->pxa_intr != PXA2X0_INT_HWUART)
 			return (0);
+		gpioconf = CPU_IS_PXA250 ? pxa25x_com_hwuart_gpioconf :
+			    pxa27x_com_hwuart_gpioconf;
 		break;
 
 	default:
 		return (0);
 	}
+	for (i = 0; gpioconf[i].pin != -1; i++) {
+		gpio = pxa2x0_gpio_get_function(gpioconf[i].pin);
+		if (GPIO_FN(gpio) != GPIO_FN(gpioconf[i].value) ||
+		    GPIO_FN_IS_OUT(gpio) != GPIO_FN_IS_OUT(gpioconf[i].value))
+			return (0);
+	}
 
 	pxa->pxa_size = 0x20;
 
Index: arm/xscale/pxa2x0_gpio.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0_gpio.c,v
retrieving revision 1.7
diff -u -r1.7 pxa2x0_gpio.c
--- arm/xscale/pxa2x0_gpio.c	17 Dec 2006 16:03:33 -0000	1.7
+++ arm/xscale/pxa2x0_gpio.c	8 Aug 2007 07:47:04 -0000
@@ -670,3 +670,248 @@
 
 	splx(s);
 }
+
+
+#if defined(CPU_XSCALE_PXA250)
+/*
+ * Configurations of GPIO for PXA25x
+ */
+struct pxa2x0_gpioconf pxa25x_com_btuart_gpioconf[] = {
+	{ 42, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* BTRXD */
+	{ 43, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* BTTXD */
+
+#if 0	/* optional */
+	{ 44, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* BTCTS */
+	{ 45, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* BTRTS */
+#endif
+
+	{ -1 }
+};
+
+struct pxa2x0_gpioconf pxa25x_com_ffuart_gpioconf[] = {
+	{ 34, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* FFRXD */
+
+#if 0	/* optional */
+	{ 35, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* CTS */
+	{ 36, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* DCD */
+	{ 37, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* DSR */
+	{ 38, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* RI */
+#endif
+
+	{ 39, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* FFTXD */
+
+#if 0	/* optional */
+	{ 40, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* DTR */
+	{ 41, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* RTS */
+#endif
+
+	{ -1 }
+};
+
+struct pxa2x0_gpioconf pxa25x_com_hwuart_gpioconf[] = {
+#if 0	/* We can select and/or. */
+	{ 42, GPIO_CLR | GPIO_ALT_FN_3_IN },	/* HWRXD */
+	{ 49, GPIO_CLR | GPIO_ALT_FN_2_IN },	/* HWRXD */
+
+	{ 43, GPIO_CLR | GPIO_ALT_FN_3_OUT },	/* HWTXD */
+	{ 48, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* HWTXD */
+
+#if 0	/* optional */
+	{ 44, GPIO_CLR | GPIO_ALT_FN_3_IN },	/* HWCST */
+	{ 51, GPIO_CLR | GPIO_ALT_FN_3_IN },	/* HWCST */
+
+	{ 45, GPIO_CLR | GPIO_ALT_FN_3_OUT },	/* HWRST */
+	{ 52, GPIO_CLR | GPIO_ALT_FN_3_OUT },	/* HWRST */
+#endif
+#endif
+
+	{ -1 }
+};
+
+struct pxa2x0_gpioconf pxa25x_com_stuart_gpioconf[] = {
+	{ 46, GPIO_CLR | GPIO_ALT_FN_2_IN },	/* RXD */
+	{ 47, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* TXD */
+	{ -1 }
+};
+
+struct pxa2x0_gpioconf pxa25x_i2c_gpioconf[] = {
+	{ -1 }
+};
+
+struct pxa2x0_gpioconf pxa25x_i2s_gpioconf[] = {
+	{ 28, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* BITCLK */
+	{ 29, GPIO_CLR | GPIO_ALT_FN_2_IN },	/* SDATA_IN */
+	{ 30, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* SDATA_OUT */
+	{ 31, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* SYNC */
+	{ 32, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* SYSCLK */
+	{ -1 }
+};
+
+struct pxa2x0_gpioconf pxa25x_pcic_gpioconf[] = {
+	{ 48, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPOE */
+	{ 49, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPWE */
+	{ 50, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPIOR */
+	{ 51, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPIOW */
+
+#if 0	/* We can select and/or. */
+	{ 52, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPCE1 */
+	{ 53, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPCE2 */
+#endif
+
+	{ 54, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* pSKTSEL */
+	{ 55, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPREG */
+	{ 56, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* nPWAIT */
+	{ 57, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* nIOIS16 */
+	{ -1 }
+};
+
+struct pxa2x0_gpioconf pxa25x_pxaacu_gpioconf[] = {
+	{ 28, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* BITCLK */
+	{ 30, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* SDATA_OUT */
+	{ 31, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* SYNC */
+
+#if 0	/* We can select and/or. */
+	{ 29, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* SDATA_IN0 */
+	{ 32, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* SDATA_IN1 */
+#endif
+
+	{ -1 }
+};
+#endif
+
+#if defined(CPU_XSCALE_PXA270)
+/*
+ * Configurations of GPIO for PXA27x
+ */
+struct pxa2x0_gpioconf pxa27x_com_btuart_gpioconf[] = {
+	{  42, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* BTRXD */
+	{  43, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* BTTXD */
+
+#if 0	/* optional */
+	{  44, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* BTCTS */
+	{  45, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* BTRTS */
+#endif
+
+	{  -1 }
+};
+
+struct pxa2x0_gpioconf pxa27x_com_ffuart_gpioconf[] = {
+#if 0	/* We can select and/or. */
+	{  16, GPIO_CLR | GPIO_ALT_FN_3_OUT },	/* FFTXD */
+	{  37, GPIO_CLR | GPIO_ALT_FN_3_OUT },	/* FFTXD */
+	{  39, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* FFTXD */
+	{  83, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* FFTXD */
+	{  99, GPIO_CLR | GPIO_ALT_FN_3_OUT },	/* FFTXD */
+
+	{  19, GPIO_CLR | GPIO_ALT_FN_3_IN },	/* FFRXD */
+	{  33, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* FFRXD */
+	{  34, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* FFRXD */
+	{  41, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* FFRXD */
+	{  53, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* FFRXD */
+	{  85, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* FFRXD */
+	{  96, GPIO_CLR | GPIO_ALT_FN_3_IN },	/* FFRXD */
+	{ 102, GPIO_CLR | GPIO_ALT_FN_3_IN },	/* FFRXD */
+
+	{   9, GPIO_CLR | GPIO_ALT_FN_3_IN },	/* FFCTS */
+	{  26, GPIO_CLR | GPIO_ALT_FN_3_IN },	/* FFCTS */
+	{  35, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* FFCTS */
+	{ 100, GPIO_CLR | GPIO_ALT_FN_3_IN },	/* FFCTS */
+
+	{  27, GPIO_CLR | GPIO_ALT_FN_3_OUT },	/* FFRTS */
+	{  41, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* FFRTS */
+	{  83, GPIO_CLR | GPIO_ALT_FN_3_OUT },	/* FFRTS */
+	{  98, GPIO_CLR | GPIO_ALT_FN_3_OUT },	/* FFRTS */
+
+	{  40, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* FFDTR */
+	{  82, GPIO_CLR | GPIO_ALT_FN_3_OUT },	/* FFDTR */
+
+	{  36, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* FFDCD */
+
+	{  33, GPIO_CLR | GPIO_ALT_FN_2_IN },	/* FFDSR */
+	{  37, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* FFDSR */
+
+	{  38, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* FFRI */
+#endif
+	{  -1 }
+};
+
+struct pxa2x0_gpioconf pxa27x_com_hwuart_gpioconf[] = {
+	{  -1 }
+};
+
+struct pxa2x0_gpioconf pxa27x_com_stuart_gpioconf[] = {
+	{  46, GPIO_CLR | GPIO_ALT_FN_2_IN },	/* STD_RXD */
+	{  47, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* STD_TXD */
+	{  -1 }
+};
+
+struct pxa2x0_gpioconf pxa27x_i2c_gpioconf[] = {
+	{ 117, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* SCL */
+	{ 118, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* SDA */
+	{  -1 }
+};
+
+struct pxa2x0_gpioconf pxa27x_i2s_gpioconf[] = {
+	{  28, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* I2S_BITCLK */
+	{  29, GPIO_CLR | GPIO_ALT_FN_2_IN },	/* I2S_SDATA_IN */
+	{  30, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* I2S_SDATA_OUT */
+	{  31, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* I2S_SYNC */
+	{ 113, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* I2S_SYSCLK */
+	{  -1 }
+};
+
+struct pxa2x0_gpioconf pxa27x_pcic_gpioconf[] = {
+	{  48, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPOE */
+	{  49, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPWE */
+	{  50, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPIOR */
+	{  51, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPIOW */
+	{  55, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPREG */
+	{  56, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* nPWAIT */
+	{  57, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* nIOIS16 */
+	{ 104, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* pSKTSEL */
+
+#if 0	/* We can select and/or. */
+	{  85, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* nPCE1 */
+	{  86, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* nPCE1 */
+	{ 102, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* nPCE1 */
+
+	{  54, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* nPCE2 */
+	{  78, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* nPCE2 */
+	{ 105, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* nPCE2 */
+#endif
+
+	{  -1 }
+};
+
+struct pxa2x0_gpioconf pxa27x_pxaacu_gpioconf[] = {
+	{  28, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* BITCLK */
+	{  30, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* SDATA_OUT */
+
+#if 0	/* We can select and/or. */
+	{  31, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* SYNC */
+	{  94, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* SYNC */
+
+	{  29, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* SDATA_IN0 */
+	{ 116, GPIO_CLR | GPIO_ALT_FN_2_IN },	/* SDATA_IN0 */
+
+	{  32, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* SDATA_IN1 */
+	{  99, GPIO_CLR | GPIO_ALT_FN_2_IN },	/* SDATA_IN1 */
+
+	{  95, GPIO_CLR | GPIO_ALT_FN_1_OUT },	/* RESET_n */
+	{ 113, GPIO_CLR | GPIO_ALT_FN_2_OUT },	/* RESET_n */
+#endif
+
+	{  -1 }
+};
+#endif
+
+void
+pxa2x0_gpio_config(struct pxa2x0_gpioconf **conflist)
+{
+	int i, j;
+
+	for (i = 0; conflist[i] != NULL; i++)
+		for (j = 0; conflist[i][j].pin != -1; j++)
+			pxa2x0_gpio_set_function(conflist[i][j].pin,
+			    conflist[i][j].value);
+}
Index: arm/xscale/pxa2x0_gpio.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0_gpio.h,v
retrieving revision 1.2
diff -u -r1.2 pxa2x0_gpio.h
--- arm/xscale/pxa2x0_gpio.h	16 Dec 2006 03:38:09 -0000	1.2
+++ arm/xscale/pxa2x0_gpio.h	8 Aug 2007 07:47:04 -0000
@@ -67,4 +67,29 @@
 extern void pxa2x0_gpio_intr_unmask(void *);
 extern void pxa2x0_gpio_set_intr_level(u_int, int);
 
+
+struct pxa2x0_gpioconf {
+	int pin;
+	u_int value;
+};
+void pxa2x0_gpio_config(struct pxa2x0_gpioconf **);
+
+extern struct pxa2x0_gpioconf pxa25x_com_ffuart_gpioconf[];
+extern struct pxa2x0_gpioconf pxa25x_com_stuart_gpioconf[];
+extern struct pxa2x0_gpioconf pxa25x_com_btuart_gpioconf[];
+extern struct pxa2x0_gpioconf pxa25x_com_hwuart_gpioconf[];
+extern struct pxa2x0_gpioconf pxa25x_i2c_gpioconf[];
+extern struct pxa2x0_gpioconf pxa25x_i2s_gpioconf[];
+extern struct pxa2x0_gpioconf pxa25x_pcic_gpioconf[];
+extern struct pxa2x0_gpioconf pxa25x_pxaacu_gpioconf[];
+
+extern struct pxa2x0_gpioconf pxa27x_com_ffuart_gpioconf[];
+extern struct pxa2x0_gpioconf pxa27x_com_stuart_gpioconf[];
+extern struct pxa2x0_gpioconf pxa27x_com_btuart_gpioconf[];
+extern struct pxa2x0_gpioconf pxa27x_com_hwuart_gpioconf[];
+extern struct pxa2x0_gpioconf pxa27x_i2c_gpioconf[];
+extern struct pxa2x0_gpioconf pxa27x_i2s_gpioconf[];
+extern struct pxa2x0_gpioconf pxa27x_pcic_gpioconf[];
+extern struct pxa2x0_gpioconf pxa27x_pxaacu_gpioconf[];
+
 #endif /* _PXA2X0_GPIO_H */
Index: arm/xscale/pxa2x0_i2c.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0_i2c.c,v
retrieving revision 1.1
diff -u -r1.1 pxa2x0_i2c.c
--- arm/xscale/pxa2x0_i2c.c	17 Dec 2006 16:03:33 -0000	1.1
+++ arm/xscale/pxa2x0_i2c.c	8 Aug 2007 07:47:04 -0000
@@ -45,13 +45,6 @@
 	bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_size,
 	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
 
-	/*
-	 * Configure the alternate functions.  The _IN is arbitrary, as the
-	 * direction is managed by the I2C unit when comms are in progress.
-	 */
-	pxa2x0_gpio_set_function(117, GPIO_ALT_FN_1_IN);	/* SCL */
-	pxa2x0_gpio_set_function(118, GPIO_ALT_FN_1_IN);	/* SDA */
-
 	pxa2x0_i2c_init(sc);
 
 	return 0;
Index: arm/xscale/pxa2x0_i2s.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/xscale/pxa2x0_i2s.c,v
retrieving revision 1.5
diff -u -r1.5 pxa2x0_i2s.c
--- arm/xscale/pxa2x0_i2s.c	26 Jun 2007 15:08:42 -0000	1.5
+++ arm/xscale/pxa2x0_i2s.c	8 Aug 2007 07:47:04 -0000
@@ -82,12 +82,6 @@
 	bus_space_barrier(sc->sc_iot, sc->sc_ioh, 0, sc->sc_size,
 	    BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
 
-	pxa2x0_gpio_set_function(28, GPIO_ALT_FN_1_OUT);  /* I2S_BITCLK */
-	pxa2x0_gpio_set_function(113, GPIO_ALT_FN_1_OUT); /* I2S_SYSCLK */
-	pxa2x0_gpio_set_function(31, GPIO_ALT_FN_1_OUT);  /* I2S_SYNC */
-	pxa2x0_gpio_set_function(30, GPIO_ALT_FN_1_OUT);  /* I2S_SDATA_OUT */
-	pxa2x0_gpio_set_function(29, GPIO_ALT_FN_2_IN);   /* I2S_SDATA_IN */
-
 	pxa2x0_i2s_init(sc);
 
 	return 0;
Index: evbarm/g42xxeb/g42xxeb_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/g42xxeb/g42xxeb_machdep.c,v
retrieving revision 1.10
diff -u -r1.10 g42xxeb_machdep.c
--- evbarm/g42xxeb/g42xxeb_machdep.c	24 Nov 2006 22:04:22 -0000	1.10
+++ evbarm/g42xxeb/g42xxeb_machdep.c	8 Aug 2007 07:47:05 -0000
@@ -261,6 +261,23 @@
 int comcnspeed = CONSPEED;
 int comcnmode = CONMODE;
 
+static struct pxa2x0_gpioconf boarddep_gpioconf[] = {
+	{ 44, GPIO_ALT_FN_1_IN },	/* BTCST */
+	{ 45, GPIO_ALT_FN_2_OUT },	/* BTRST */
+
+	{ -1 }
+};
+static struct pxa2x0_gpioconf *g42xxeb_gpioconf[] = {
+	pxa25x_com_btuart_gpioconf,
+	pxa25x_com_ffuart_gpioconf,
+#if 0
+	pxa25x_com_stuart_gpioconf,
+	pxa25x_pxaacu_gpioconf,
+#endif
+	boarddep_gpioconf,
+	NULL
+};
+
 /*
  * void cpu_reboot(int howto, char *bootstr)
  *
@@ -498,10 +515,7 @@
 
 	/* setup GPIO for BTUART, in case bootloader doesn't take care of it */
 	pxa2x0_gpio_bootstrap(G42XXEB_GPIO_VBASE);
-	pxa2x0_gpio_set_function(42, GPIO_ALT_FN_1_IN);
-	pxa2x0_gpio_set_function(43, GPIO_ALT_FN_2_OUT);
-	pxa2x0_gpio_set_function(44, GPIO_ALT_FN_1_IN);
-	pxa2x0_gpio_set_function(45, GPIO_ALT_FN_2_OUT);
+	pxa2x0_gpio_config(g42xxeb_gpioconf);
 
 	LEDSTEP();
 
Index: evbarm/gumstix/gxio.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/gumstix/gxio.c,v
retrieving revision 1.4
diff -u -r1.4 gxio.c
--- evbarm/gumstix/gxio.c	20 Apr 2007 13:00:08 -0000	1.4
+++ evbarm/gumstix/gxio.c	8 Aug 2007 07:47:06 -0000
@@ -52,10 +52,6 @@
 #include "locators.h"
 
 
-struct gpioconf {
-	int pin;
-	u_int value;
-};
 struct gxioconf {
 	const char *name;
 	void (*config)(void);
@@ -80,32 +76,18 @@
 CFATTACH_DECL(
     gxio, sizeof(struct gxio_softc), gxiomatch, gxioattach, NULL, NULL);
 
-char busheader[MAX_BOOT_STRING]; 
+char busheader[MAX_BOOT_STRING];
 
-struct gpioconf gpioconf[] = {
+static struct pxa2x0_gpioconf boarddep_gpioconf[] = {
 	/* Bluetooth module configuration */
 	{  7, GPIO_OUT | GPIO_SET },	/* power on */
 	{ 12, GPIO_ALT_FN_1_OUT },	/* 32kHz out. required by SingleStone */
 
 	/* AC97 configuration */
-#if 1
-	/* this configuration set by pxaacu_attach()::pxa2x0_ac97.c */
-#else
-	/* Don't reorder */
-	{ 31, GPIO_ALT_FN_2_OUT },	/* SYNC */
-	{ 30, GPIO_ALT_FN_2_OUT },	/* SDATA_OUT */
-	{ 28, GPIO_ALT_FN_1_IN },	/* BITCLK */
-	{ 29, GPIO_ALT_FN_1_IN },	/* SDATA_IN0 */
-#endif
-
-	/* FFUART configuration : is connected only TXD/RXD */
-	{ 34, GPIO_ALT_FN_1_IN },	/* FFRXD */
-	{ 39, GPIO_ALT_FN_2_OUT },	/* FFTXD */
+	{ 29, GPIO_CLR | GPIO_ALT_FN_1_IN },	/* SDATA_IN0 */
 
 #ifndef GXIO_BLUETOOTH_ON_HWUART
 	/* BTUART configuration */
-	{ 42, GPIO_ALT_FN_1_IN },	/* BTRXD */
-	{ 43, GPIO_ALT_FN_2_OUT },	/* BTTXD */
 	{ 44, GPIO_ALT_FN_1_IN },	/* BTCST */
 	{ 45, GPIO_ALT_FN_2_OUT },	/* BTRST */
 #else
@@ -116,10 +98,6 @@
 	{ 45, GPIO_ALT_FN_3_OUT },	/* HWRST */
 #endif
 
-	/* STUART configuration : is connected only TXD/RXD */
-	{ 46, GPIO_ALT_FN_2_IN },	/* RXD */
-	{ 47, GPIO_ALT_FN_1_OUT },	/* TXD */
-
 #ifndef GXIO_BLUETOOTH_ON_HWUART
 	/* HWUART configuration */
 	{ 48, GPIO_ALT_FN_1_OUT },	/* HWTXD */
@@ -220,14 +198,24 @@
 void
 gxio_config_pin()
 {
-	int i;
+	struct pxa2x0_gpioconf *gumstix_gpioconf[] = {
+		pxa25x_com_ffuart_gpioconf,
+		pxa25x_com_stuart_gpioconf,
+#ifndef GXIO_BLUETOOTH_ON_HWUART
+		pxa25x_com_btuart_gpioconf,
+#endif
+		pxa25x_com_hwuart_gpioconf,
+		pxa25x_i2c_gpioconf,
+		pxa25x_pxaacu_gpioconf,
+		boarddep_gpioconf,
+		NULL
+	};
 
 	/* XXX: turn off for power of bluetooth module */
 	pxa2x0_gpio_set_function(7, GPIO_OUT | GPIO_CLR);
 	delay(100);
 
-	for (i = 0; gpioconf[i].pin != -1; i++)
-		pxa2x0_gpio_set_function(gpioconf[i].pin, gpioconf[i].value);
+	pxa2x0_gpio_config(gumstix_gpioconf);
 }
 
 void
Index: evbarm/lubbock/lubbock_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/lubbock/lubbock_machdep.c,v
retrieving revision 1.14
diff -u -r1.14 lubbock_machdep.c
--- evbarm/lubbock/lubbock_machdep.c	24 Nov 2006 22:04:22 -0000	1.14
+++ evbarm/lubbock/lubbock_machdep.c	8 Aug 2007 07:47:06 -0000
@@ -266,6 +266,26 @@
 int comcnspeed = CONSPEED;
 int comcnmode = CONMODE;
 
+static struct pxa2x0_gpioconf boarddep_gpioconf[] = {
+	{ 44, GPIO_ALT_FN_1_IN },	/* BTCST */
+	{ 45, GPIO_ALT_FN_2_OUT },	/* BTRST */
+
+	{ 29, GPIO_ALT_FN_1_IN },	/* SDATA_IN0 */
+
+	{ -1 }
+};
+static struct pxa2x0_gpioconf *lubbock_gpioconf[] = {
+	pxa25x_com_btuart_gpioconf,
+	pxa25x_com_ffuart_gpioconf,
+#if 0
+	pxa25x_com_stuart_gpioconf,
+#endif
+	pxa25x_pcic_gpioconf,
+	pxa25x_pxaacu_gpioconf,
+	boarddep_gpioconf,
+	NULL
+};
+
 /*
  * void cpu_reboot(int howto, char *bootstr)
  *
@@ -509,10 +529,7 @@
 
 	/* setup GPIO for BTUART, in case bootloader doesn't take care of it */
 	pxa2x0_gpio_bootstrap(LUBBOCK_GPIO_VBASE);
-	pxa2x0_gpio_set_function(42, GPIO_ALT_FN_1_IN);
-	pxa2x0_gpio_set_function(43, GPIO_ALT_FN_2_OUT);
-	pxa2x0_gpio_set_function(44, GPIO_ALT_FN_1_IN);
-	pxa2x0_gpio_set_function(45, GPIO_ALT_FN_2_OUT);
+	pxa2x0_gpio_config(lubbock_gpioconf);
 
 	/* turn on clock to UART block.
 	   XXX: this should not be done here. */
Index: evbarm/viper/viper_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/viper/viper_machdep.c,v
retrieving revision 1.6
diff -u -r1.6 viper_machdep.c
--- evbarm/viper/viper_machdep.c	24 Nov 2006 22:04:22 -0000	1.6
+++ evbarm/viper/viper_machdep.c	8 Aug 2007 07:47:07 -0000
@@ -265,6 +265,20 @@
 int comcnspeed = CONSPEED;
 int comcnmode = CONMODE;
 
+static struct pxa2x0_gpioconf boarddep_gpioconf[] = {
+	{ 44, GPIO_ALT_FN_1_IN },	/* BTCST */
+	{ 45, GPIO_ALT_FN_2_OUT },	/* BTRST */
+
+	{ -1 } 
+};
+static struct pxa2x0_gpioconf *viper_gpioconf[] = {
+	pxa25x_com_btuart_gpioconf,
+	pxa25x_com_ffuart_gpioconf,
+	pxa25x_com_stuart_gpioconf,
+	boarddep_gpioconf,
+	NULL
+};
+
 /*
  * void cpu_reboot(int howto, char *bootstr)
  *
@@ -429,10 +443,7 @@
 
 	/* setup GPIO for BTUART, in case bootloader doesn't take care of it */
 	pxa2x0_gpio_bootstrap(VIPER_GPIO_VBASE);
-	pxa2x0_gpio_set_function(42, GPIO_ALT_FN_1_IN);
-	pxa2x0_gpio_set_function(43, GPIO_ALT_FN_2_OUT);
-	pxa2x0_gpio_set_function(44, GPIO_ALT_FN_1_IN);
-	pxa2x0_gpio_set_function(45, GPIO_ALT_FN_2_OUT);
+	pxa2x0_gpio_config(viper_gpioconf);
 
 	/* turn on clock to UART block.
 	   XXX: this should not be done here. */
Index: zaurus/zaurus/machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/zaurus/zaurus/machdep.c,v
retrieving revision 1.5
diff -u -r1.5 machdep.c
--- zaurus/zaurus/machdep.c	28 Jun 2007 16:07:12 -0000	1.5
+++ zaurus/zaurus/machdep.c	8 Aug 2007 07:47:14 -0000
@@ -255,6 +255,63 @@
 void	kgdb_port_init(void);
 #endif
 
+#if defined(CPU_XSCALE_PXA250)
+static struct pxa2x0_gpioconf pxa25x_boarddep_gpioconf[] = {
+	{  34, GPIO_ALT_FN_1_IN },	/* FFRXD */
+	{  35, GPIO_ALT_FN_1_IN },	/* FFCTS */
+	{  39, GPIO_ALT_FN_2_OUT },	/* FFTXD */
+	{  40, GPIO_ALT_FN_2_OUT },	/* FFDTR */
+	{  41, GPIO_ALT_FN_2_OUT },	/* FFRTS */
+
+	{  44, GPIO_ALT_FN_1_IN },	/* BTCST */
+	{  45, GPIO_ALT_FN_2_OUT },	/* BTRST */
+
+	{ -1 }
+};
+static struct pxa2x0_gpioconf *pxa25x_zaurus_gpioconf[] = {
+	pxa25x_com_btuart_gpioconf,
+	pxa25x_com_ffuart_gpioconf,
+	pxa25x_com_stuart_gpioconf,
+	pxa25x_boarddep_gpioconf,
+	NULL
+};
+#else
+static struct pxa2x0_gpioconf *pxa25x_zaurus_gpioconf[] = {
+	NULL
+};
+#endif
+#if defined(CPU_XSCALE_PXA270)
+static struct pxa2x0_gpioconf pxa27x_boarddep_gpioconf[] = {
+	{  34, GPIO_ALT_FN_1_IN },	/* FFRXD */
+	{  35, GPIO_ALT_FN_1_IN },	/* FFCTS */
+	{  39, GPIO_ALT_FN_2_OUT },	/* FFTXD */
+	{  40, GPIO_ALT_FN_2_OUT },	/* FFDTR */
+	{  41, GPIO_ALT_FN_2_OUT },	/* FFRTS */
+
+	{  44, GPIO_ALT_FN_1_IN },	/* BTCST */
+	{  45, GPIO_ALT_FN_2_OUT },	/* BTRST */
+
+	{  31, GPIO_ALT_FN_2_OUT },	/* SYNC */
+	{  29, GPIO_ALT_FN_1_IN },	/* SDATA_IN0 */
+
+	{ -1 }
+};
+static struct pxa2x0_gpioconf *pxa27x_zaurus_gpioconf[] = {
+	pxa27x_com_btuart_gpioconf,
+	pxa27x_com_ffuart_gpioconf,
+	pxa27x_com_stuart_gpioconf,
+	pxa27x_pxaacu_gpioconf,
+	pxa27x_i2c_gpioconf,
+	pxa27x_i2s_gpioconf,
+	pxa27x_boarddep_gpioconf,
+	NULL
+};
+#else
+static struct pxa2x0_gpioconf *pxa27x_zaurus_gpioconf[] = {
+	NULL
+};
+#endif
+
 /*
  * void cpu_reboot(int howto, char *bootstr)
  *
@@ -501,6 +558,7 @@
 	pv_addr_t kernel_l1pt;
 	paddr_t memstart;
 	psize_t memsize;
+	struct pxa2x0_gpioconf **zaurus_gpioconf;
 
 	/* Get ready for zaurus_restart() */
 	pxa2x0_memctl_bootstrap(PXA2X0_MEMCTL_BASE);
@@ -540,13 +598,17 @@
 	 * This test will work for now but has to be revised when support
 	 * for other models is added.
 	 */
-	if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X)
+	if ((cputype & ~CPU_ID_XSCALE_COREREV_MASK) == CPU_ID_PXA27X) {
 		zaurusmod = ZAURUS_C3000;
-	else
+		zaurus_gpioconf = pxa27x_zaurus_gpioconf;
+	} else {
 		zaurusmod = ZAURUS_C860;
+		zaurus_gpioconf = pxa25x_zaurus_gpioconf;
+	}
 
 	/* setup a serial console for very early boot */
 	pxa2x0_gpio_bootstrap(ZAURUS_GPIO_VBASE);
+	pxa2x0_gpio_config(zaurus_gpioconf);
 	pxa2x0_clkman_bootstrap(ZAURUS_CLKMAN_VBASE);
 	if (strcmp(console, "glass") != 0)
 		consinit();
@@ -1076,23 +1138,12 @@
 	if (strcmp(console, "ffuart") == 0) {
 		paddr = PXA2X0_FFUART_BASE;
 		cken = CKEN_FFUART;
-		pxa2x0_gpio_set_function(34, GPIO_ALT_FN_1_IN);
-		pxa2x0_gpio_set_function(39, GPIO_ALT_FN_2_OUT);
-		pxa2x0_gpio_set_function(35, GPIO_ALT_FN_1_IN);
-		pxa2x0_gpio_set_function(40, GPIO_ALT_FN_2_OUT);
-		pxa2x0_gpio_set_function(41, GPIO_ALT_FN_2_OUT);
 	} else if (strcmp(console, "btuart") == 0) {
 		paddr = PXA2X0_BTUART_BASE;
 		cken = CKEN_BTUART;
-		pxa2x0_gpio_set_function(42, GPIO_ALT_FN_1_IN);
-		pxa2x0_gpio_set_function(43, GPIO_ALT_FN_2_OUT);
-		pxa2x0_gpio_set_function(44, GPIO_ALT_FN_1_IN);
-		pxa2x0_gpio_set_function(45, GPIO_ALT_FN_2_OUT);
 	} else if (strcmp(console, "stuart") == 0) {
 		paddr = PXA2X0_STUART_BASE;
 		cken = CKEN_STUART;
-		pxa2x0_gpio_set_function(46, GPIO_ALT_FN_2_IN);
-		pxa2x0_gpio_set_function(47, GPIO_ALT_FN_1_OUT);
 		irda_on(0);
 	} else
 #endif
@@ -1124,23 +1175,12 @@
 	if (strcmp(kgdb_devname, "ffuart") == 0) {
 		paddr = PXA2X0_FFUART_BASE;
 		cken = CKEN_FFUART;
-		pxa2x0_gpio_set_function(34, GPIO_ALT_FN_1_IN);
-		pxa2x0_gpio_set_function(39, GPIO_ALT_FN_2_OUT);
-		pxa2x0_gpio_set_function(35, GPIO_ALT_FN_1_IN);
-		pxa2x0_gpio_set_function(40, GPIO_ALT_FN_2_OUT);
-		pxa2x0_gpio_set_function(41, GPIO_ALT_FN_2_OUT);
 	} else if (strcmp(kgdb_devname, "btuart") == 0) {
 		paddr = PXA2X0_BTUART_BASE;
 		cken = CKEN_BTUART;
-		pxa2x0_gpio_set_function(42, GPIO_ALT_FN_1_IN);
-		pxa2x0_gpio_set_function(43, GPIO_ALT_FN_2_OUT);
-		pxa2x0_gpio_set_function(44, GPIO_ALT_FN_1_IN);
-		pxa2x0_gpio_set_function(45, GPIO_ALT_FN_2_OUT);
 	} else if (strcmp(kgdb_devname, "stuart") == 0) {
 		paddr = PXA2X0_STUART_BASE;
 		cken = CKEN_STUART;
-		pxa2x0_gpio_set_function(46, GPIO_ALT_FN_2_IN);
-		pxa2x0_gpio_set_function(47, GPIO_ALT_FN_1_OUT);
 		irda_on(0);
 	} else
 		return;

----Next_Part(Wed_Aug__8_17_36_32_2007_124)----