Subject: Re: armv6 - Thread and process ID registers
To: None <email@example.com>
From: Matt Thomas <firstname.lastname@example.org>
Date: 07/09/2007 15:17:50
Richard Earnshaw wrote:
> On Mon, 2007-07-09 at 13:31 -0700, Matt Thomas wrote:
>> The ARM1136 has three new coprocessor 32-bit (of coures) registers for storing
>> thread and process information.
>> They are user read/write, user read/only, and privileged-only read/write.
>> Obviously the user-visible ones need to dealt with on a context switch. But the
>> problem is cf_context_switch doesn't anywhere to store the user readwrite
>> register (it only gets passed the L1 page table ptr). It doesn't seem smart to
>> store/restore it on user exceptions since it'll only change on context switches.
>> Since r4 stores the old lwp, I'm thinking of using that register to store it
>> in mdlwp.
> I think the user-space registers can be hidden/disabled if we don't want
> to support them immediately. We should do this if we can't guarantee to
> save/restore the value on context switches at this time.
Didn't find a bit to do that.
>> For the user readonly register, I would also keep that in mdlwp and restore it
>> in cf_context_switch. But I'm not sure what user space would make it. I'd
>> allow a user to store a value in it via sysarch(ARM_SET_USERID, value).
> Linux uses it (or is it the R/W one?) for Thread local storage (and gcc
> has a TLS usage model to use it for that).
TLS support seemed the most probable use. Thought about that after I sent the
mail. For platforms that don't support it, should we emulate the MRC for it
or rely on the user code doing the right thing?
Thanks for the comments.