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Dear Richard, dear folks,

i'm confused about the correct procedure concerning MMU disabling on ARMv3 
and ARMv4. The data sheets i have for ARM610/ARM710 and SA don't mention 
what effect it will have on the instruction fetching. AFAIK its two 
instructions that are in the pipeline before the translation becomes 
effective.

The offending code is in src/sys/arch/acorn32/stand/boot32/start.S around 
line 83. Will the following patch fix the problem? or is something really 
wrong and should i split off ARMv3 and ARMv4 mmu disable code?

Index: start.S
===================================================================
RCS file: /cvsroot/src/sys/arch/acorn32/stand/boot32/start.S,v
retrieving revision 1.1
diff -u -r1.1 start.S
--- start.S     28 Dec 2002 23:57:37 -0000      1.1
+++ start.S     3 Jul 2007 15:51:02 -0000
@@ -81,8 +81,9 @@
        orr     r0, r0, #CPU_CONTROL_LABT_ENABLE | CPU_CONTROL_32BD_ENABLE 
| CPU_CONTROL_32BP_ENABLE
        mov     r13, r0                                                 /* save this control value in r13       */
        cmp     r14, #0
+       mcrne   15, 0, r0, c7, c5, 0                                    /* flush ARMv4 I cache                  */
        mcr     15, 0, r0, c1, c0, 0                                    /* write control register!              */
-/*1*/  mcrne   15, 0, r1, c7, c5, 0                                    /* write zero in ARMv4 MMU disable      */
+/*1*/  mov     r0, r0                                                  /* NOP                                  */
 /*2*/  mov     pc, r9                                                  /* branch to physical address           */
 
 relocate_code_physical_restart:

(r9 contains the physical address of relocate_code_physical_restart)

Would you like to have have a look at the start.S MMU code? i'd be very 
gratefull if we can get this piece of code right for once and for all.

With regards,
Reinoud


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