Subject: Re: Can I access ISA bus and PGIO pins through /dev/mem?
To: Anders Lindgren <email@example.com>
From: Jesse Off <joff@embeddedARM.com>
Date: 06/11/2007 13:36:13
Anders Lindgren wrote:
> Hi everyone, and especially Jesse Off if you're reading. :-)
> Playing around with my TS7250 board and its TS7KV framebuffer, and
> NetBSD 4.99.20.
> I am trying to access the fb on the PC/104 bus from user space by
> simply mmap:ing /dev/mem, following the board's [Linux] example code.
> This way, I've been able to identify the board on the bus, load the FPGA
> bitmask into the FPGA, ACK the loading, and activate the FPGA. It lights
> its green LED. :-) However, I get no visible video output apart from a
> brief flicker before the screen goes blank again.
Likely, all you need to do is enable vsync/hsync in the control
register. On FPGA bitstream load, those bits are cleared so the monitor
will be in power-save. Otherwise, you'd be seeing uninitialized SDRAM
until you got around to zeroing out the frame buffer.
> Before I dig any deeper into this -- is this method going to work at
> all? I've seen comments to the effect that some X drivers do pretty much
> this, and I'd like to use the same method to bang on some EP9302 GPIO
> pins as well. Or do I have to modify the tsarm startup or write a stub
> open + mmap driver somehow to tell NetBSD not to cache these address
It should map them uncacheable/unbufferable. If you request an address
that falls in SDRAM, I think only then you will get cacheable/bufferable
> As long as the kernel realizes that the physical ISA addresses I mmap
> are non-cachable side effect memory locations, it should Just Work(tm)?
> I figured the tsarm "isaio" node somehow takes care of this somewhere
> during startup, but reading the code didn't tell me much, as I am not
> yet familiar with how the bus space framework works.
Not quite. I believe the ARM pmap module (pmap_enter()) will assume any
physical address not explicitly registered with uvm_physload() is