Subject: Re: structuring interrupt machine in ppoea-renovation
To: Chris Gilbert <>
From: Toru Nishimura <>
List: port-arm
Date: 05/11/2007 11:33:32
Chris Giberts sez;

> I'd like to think other arm hardware can switch to it quickly, eg ep93xx 
> springs to mind as being able to switch over quickly, as it's in the 
> position of having 2 banks of 32 irqs.

The following is the code excerpt I've sent to port-power@ some time

> Robert Swindells  asked;
>> How is the new interrupt code designed to be used on systems that have
>> interrupt enables and masks split over multiple registers ?

struct ipic_ops {
        struct pic_ops pic;
        uint32_t pending_events_x;    /* 8 external source */
        uint32_t pending_events_l;    /* 32 source 0..31 */
        uint32_t pending_events_h;    /* 32 source 32..63 */
        uint32_t enable_mask_x;
        uint32_t enable_mask_l;
        uint32_t enable_mask_h;

The lines is for "Intergrated PIC" found in some MPC82xx/83xx PowerQUICC
product family.  The IPC brings upto 64 independent interrupt sources from
SoC buildin peripheral devices and 8 independent sources from external
device hooked with the MPC.

The central idea of Michael's achievement is to offer an encapsulation, or
"closure" to hide wide ranging details of target HW interrupt controllers.
He provides the way to "cascade" other type of "pic_ops" to steer interrupt
delivery thru away, let's consider a case to add low key "GPIO" interrupts
from external hook.

Then whole construct is made in such a fashion of very large number of single
bit array handled and delivered by common code.  Of course it'd be _the_
place to make implementation smart and quick to run.

Toru Nishimura / ALKYL Technology /