Subject: common irq handler code
To: None <port-arm@netbsd.org>
From: Chris Gilbert <chris@dokein.co.uk>
List: port-arm
Date: 04/07/2007 20:26:40
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--------------080701050503080102070009
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Hi,
I was looking into fixing acorn32 to actually build, and found that its
IRQ handler is dated by NetBSD/arm standards (it's still in asm, it
lacks IPL_ levels etc) I was about to update it but realised that I'd
just be making yet another copy of the same code with a couple of tweaks.
So instead I've taken the footbridge irqhandler code, and made it a
common file. (The footbridge version was based on Jason's work for
xscale platforms)
To use it, you provide two functions (via machine/intr_hardware.h):
arm_hardware_set_irq_mask - sets the interrupt mask in the hardware
arm_hardware_irq_status - retrieves the current hardware interrupts.
These should be pretty simple functions for most arm hardware, on
footbridge it totals about 10 lines of code. Iomd is probably a bit
more to allow for different iomds with 16 and 32bit registers.
With this the platform intr_init, intr_claim and intr_disestablish code
will then wrapper arm_intr_init, arm_intr_claim and
arm_intr_disestablish, with any appropriate tweaks.
The common code is in arm/arm32/arm_irqhandler.c and arm/include/arm_intr.h
Limitations:
* Only works if you use 32 or less interrupts
* Need to update platforms to use it (I can do iomd and footbridge, but
lack hardware for everything else)
* soft interrupts are handled by a separate uint32, rather than using
unused bits of the software copy of the current interrupts.
* currently interrupts are serviced in bit wise order, rather than in
ipl order.
Pros:
* only one set of interrupt code for most arm ports, so less maintenance
overhead, this maybe relevant for MI changes being done for locking (eg
vmlocking, idlelwp etc)
In principle does the attached diff, and the above make sense, and more
importantly sound portable to other arm hardware?
Looking at other (more recent?) arm hardware I'm wondering if (in the
longer term) something more modular is needed. So that multiple irq
handler instances can exist, with a shared set of spl* routines and a
global current_spl_level. eg ep93xx has two sets of irq registers, add
in soft interrupts and that makes three. omap looks to have banks of
registers, so each bank could be treated individually (although it talks
about level 2 and level 1 interrupts so it may not actually fit with
something generic). Of course this may not actually simplify anything
and could underperform...
Anyway, does the idea of having generic irq handling for arm seem
sensible, and am I heading down the right track with this?
Thanks,
Chris
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Index: arm/arm32/arm_irqhandler.c
===================================================================
RCS file: arm/arm32/arm_irqhandler.c
diff -N arm/arm32/arm_irqhandler.c
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ arm/arm32/arm_irqhandler.c 7 Apr 2007 18:29:08 -0000
@@ -0,0 +1,463 @@
+/* $NetBSD: footbridge_irqhandler.c,v 1.17 2006/12/25 18:39:48 wiz Exp $ */
+
+/*
+ * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ARM_SPL_NOINLINE
+#define ARM_SPL_NOINLINE
+#endif
+
+#include <sys/cdefs.h>
+__KERNEL_RCSID(0,"$NetBSD: footbridge_irqhandler.c,v 1.17 2006/12/25 18:39:48 wiz Exp $");
+
+#include "opt_irqstats.h"
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/malloc.h>
+#include <uvm/uvm_extern.h>
+
+#include <arm/arm_intr.h>
+#include <machine/intr.h>
+#include <machine/cpu.h>
+
+/* Interrupt handler queues. */
+static struct intrq arm_intrq[ARM_INTR_NIRQ];
+
+/* Interrupts to mask at each level. */
+uint32_t arm_imask[NIPL];
+
+/* soft interrupts to mask at each level: */
+uint32_t arm_simask[NIPL];
+
+/* Software copy of the IRQs we have enabled. */
+volatile uint32_t intr_enabled;
+
+/* Current interrupt priority level */
+volatile int current_spl_level;
+
+/* current pending soft interrupts */
+volatile uint32_t arm_soft_intr_pending;
+
+/* Interrupts pending */
+volatile uint32_t arm_intr_pending;
+
+void arm_intr_dispatch(struct clockframe *frame);
+
+void arm_do_pending_soft_intr(void);
+
+#define SI_TO_BIT(si) (1U << (si))
+
+/*
+ * Map a software interrupt queue to an interrupt priority level.
+ */
+static const int si_to_ipl[SI_NQUEUES] = {
+ IPL_SOFT, /* SI_SOFT */
+ IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
+ IPL_SOFTNET, /* SI_SOFTNET */
+ IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
+};
+
+const struct evcnt *
+arm_intr_evcnt(int irq)
+{
+ /* XXX check range is valid */
+ if (irq < 0 || irq > ARM_INTR_NIRQ)
+ return NULL;
+ else
+ return &arm_intrq[irq].iq_ev;
+}
+
+static inline void
+arm_intr_enable_irq(int irq)
+{
+ intr_enabled |= (1U << irq);
+ arm_hardware_set_irq_mask(intr_enabled);
+}
+
+static inline void
+arm_intr_disable_irq(int irq)
+{
+ intr_enabled &= ~(1U << irq);
+ arm_hardware_set_irq_mask(intr_enabled);
+}
+
+/*
+ * NOTE: This routine must be called with interrupts disabled in the CPSR.
+ */
+static void
+arm_intr_calculate_masks(void)
+{
+ struct intrq *iq;
+ struct intrhand *ih;
+ int irq, ipl;
+
+ /* First, figure out which IPLs each IRQ has. */
+ for (irq = 0; irq < ARM_INTR_NIRQ; irq++) {
+ int levels = 0;
+ iq = &arm_intrq[irq];
+ arm_intr_disable_irq(irq);
+ iq->iq_ipl = 0;
+ for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
+ ih = TAILQ_NEXT(ih, ih_list))
+ {
+ levels |= (1U << ih->ih_ipl);
+ /* check if this is the highest ipl for this irq */
+ if (iq->iq_ipl < ih->ih_ipl)
+ iq->iq_ipl = ih->ih_ipl;
+ }
+ iq->iq_levels = levels;
+ }
+
+ /* Next, figure out which IRQs are used by each IPL. */
+ for (ipl = 0; ipl < NIPL; ipl++) {
+ int irqs = 0;
+ for (irq = 0; irq < ARM_INTR_NIRQ; irq++) {
+ if (arm_intrq[irq].iq_levels & (1U << ipl))
+ irqs |= (1U << irq);
+ }
+ arm_imask[ipl] = irqs;
+ }
+
+ /* IPL_NONE must open up all interrupts */
+ arm_imask[IPL_NONE] = 0;
+ arm_simask[IPL_NONE] = 0;
+
+ /*
+ * Initialize the soft interrupt masks to block themselves.
+ */
+ arm_imask[IPL_SOFT] = 0;
+ arm_simask[IPL_SOFT] = SI_TO_BIT(SI_SOFT);
+ arm_imask[IPL_SOFTCLOCK] = 0;
+ arm_simask[IPL_SOFTCLOCK] = SI_TO_BIT(SI_SOFTCLOCK);
+ arm_imask[IPL_SOFTNET] = 0;
+ arm_simask[IPL_SOFTNET] = SI_TO_BIT(SI_SOFTNET);
+ arm_imask[IPL_SOFTSERIAL] = 0;
+ arm_simask[IPL_SOFTSERIAL] = SI_TO_BIT(SI_SOFTSERIAL);
+
+ arm_imask[IPL_SOFTCLOCK] |= arm_imask[IPL_SOFT];
+ arm_simask[IPL_SOFTCLOCK] |= arm_simask[IPL_SOFT];
+ arm_imask[IPL_SOFTNET] |= arm_imask[IPL_SOFTCLOCK];
+ arm_simask[IPL_SOFTNET] |= arm_simask[IPL_SOFTCLOCK];
+
+ /*
+ * Enforce a hierarchy that gives "slow" device (or devices with
+ * limited input buffer space/"real-time" requirements) a better
+ * chance at not dropping data.
+ */
+ arm_imask[IPL_BIO] |= arm_imask[IPL_SOFTNET];
+ arm_simask[IPL_BIO] |= arm_simask[IPL_SOFTNET];
+ arm_imask[IPL_NET] |= arm_imask[IPL_BIO];
+ arm_simask[IPL_NET] |= arm_simask[IPL_BIO];
+ arm_imask[IPL_SOFTSERIAL] |= arm_imask[IPL_NET];
+ arm_simask[IPL_SOFTSERIAL] |= arm_simask[IPL_NET];
+
+ arm_imask[IPL_TTY] |= arm_imask[IPL_SOFTSERIAL];
+ arm_simask[IPL_TTY] |= arm_simask[IPL_SOFTSERIAL];
+
+ /*
+ * splvm() blocks all interrupts that use the kernel memory
+ * allocation facilities.
+ */
+ arm_imask[IPL_VM] |= arm_imask[IPL_TTY];
+ arm_simask[IPL_VM] |= arm_simask[IPL_TTY];
+
+ /*
+ * Audio devices are not allowed to perform memory allocation
+ * in their interrupt routines, and they have fairly "real-time"
+ * requirements, so give them a high interrupt priority.
+ */
+ arm_imask[IPL_AUDIO] |= arm_imask[IPL_VM];
+ arm_simask[IPL_AUDIO] |= arm_simask[IPL_VM];
+
+ /*
+ * splclock() must block anything that uses the scheduler.
+ */
+ arm_imask[IPL_CLOCK] |= arm_imask[IPL_AUDIO];
+ arm_simask[IPL_CLOCK] |= arm_simask[IPL_AUDIO];
+
+ /*
+ * footbridge has separate statclock.
+ */
+ arm_imask[IPL_STATCLOCK] |= arm_imask[IPL_CLOCK];
+ arm_simask[IPL_STATCLOCK] |= arm_simask[IPL_CLOCK];
+
+ /*
+ * splhigh() must block "everything".
+ */
+ arm_imask[IPL_HIGH] |= arm_imask[IPL_STATCLOCK];
+ arm_simask[IPL_HIGH] |= arm_simask[IPL_STATCLOCK];
+
+ /*
+ * XXX We need serial drivers to run at the absolute highest priority
+ * in order to avoid overruns, so serial > high.
+ */
+ arm_imask[IPL_SERIAL] |= arm_imask[IPL_HIGH];
+ arm_simask[IPL_SERIAL] |= arm_simask[IPL_HIGH];
+
+ /*
+ * Calculate the ipl level to go to when handling this interrupt
+ */
+ for (irq = 0; irq < ARM_INTR_NIRQ; irq++) {
+ iq = &arm_intrq[irq];
+ if (TAILQ_FIRST(&iq->iq_list) != NULL)
+ arm_intr_enable_irq(irq);
+ }
+}
+
+int
+_splraise(int ipl)
+{
+ return (arm_intr_splraise(ipl));
+}
+
+/* this will always take us to the ipl passed in */
+void
+splx(int new)
+{
+ arm_intr_splx(new);
+}
+
+int
+_spllower(int ipl)
+{
+ return (arm_intr_spllower(ipl));
+}
+
+void
+arm_do_pending_soft_intr(void)
+{
+ static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
+ uint32_t new, oldirqstate;
+
+ if (__cpu_simple_lock_try(&processing) == 0)
+ return;
+
+ new = current_spl_level;
+
+ oldirqstate = disable_interrupts(I32_bit);
+
+#define DO_SOFTINT(si) \
+ if ((arm_soft_intr_pending & ~arm_simask[new]) & SI_TO_BIT(si)) { \
+ arm_soft_intr_pending &= ~SI_TO_BIT(si); \
+ current_spl_level = si_to_ipl[(si)]; \
+ restore_interrupts(oldirqstate); \
+ softintr_dispatch(si); \
+ oldirqstate = disable_interrupts(I32_bit); \
+ current_spl_level = new; \
+ }
+ DO_SOFTINT(SI_SOFTSERIAL);
+ DO_SOFTINT(SI_SOFTNET);
+ DO_SOFTINT(SI_SOFTCLOCK);
+ DO_SOFTINT(SI_SOFT);
+
+ __cpu_simple_unlock(&processing);
+
+ restore_interrupts(oldirqstate);
+}
+
+
+/* called from splhigh, so the matching splx will set the interrupt up.*/
+void
+_setsoftintr(int si)
+{
+ int oldirqstate;
+
+ oldirqstate = disable_interrupts(I32_bit);
+ arm_soft_intr_pending |= SI_TO_BIT(si);
+ restore_interrupts(oldirqstate);
+
+ /* Process unmasked pending soft interrupts. */
+ if (arm_soft_intr_pending & ~arm_simask[current_spl_level])
+ arm_do_pending_soft_intr();
+}
+
+void
+arm_intr_init(void)
+{
+ struct intrq *iq;
+ int i;
+
+ intr_enabled = 0;
+ arm_hardware_set_irq_mask(intr_enabled);
+ current_spl_level = 0;
+ arm_intr_pending = 0;
+ arm_soft_intr_pending = 0;
+
+ for (i = 0; i < ARM_INTR_NIRQ; i++) {
+ iq = &arm_intrq[i];
+ TAILQ_INIT(&iq->iq_list);
+
+ sprintf(iq->iq_name, "irq %d", i);
+ evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
+ NULL, "arm_intr", iq->iq_name);
+ }
+
+ arm_intr_calculate_masks();
+
+ /* Enable IRQ's, we don't have any FIQ's*/
+ enable_interrupts(I32_bit);
+}
+
+void *
+arm_intr_claim(int irq, int ipl, const char *name, int (*func)(void *), void *arg)
+{
+ struct intrq *iq;
+ struct intrhand *ih;
+ u_int oldirqstate;
+
+ if (irq < 0 || irq > ARM_INTR_NIRQ)
+ panic("arm_intr_establish: IRQ %d out of range", irq);
+
+ ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
+ if (ih == NULL)
+ {
+ printf("No memory");
+ return (NULL);
+ }
+
+ ih->ih_func = func;
+ ih->ih_arg = arg;
+ ih->ih_ipl = ipl;
+ ih->ih_irq = irq;
+
+ iq = &arm_intrq[irq];
+
+ oldirqstate = disable_interrupts(I32_bit);
+
+ TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
+
+ arm_intr_calculate_masks();
+
+ /* detach the existing event counter and add the new name */
+ evcnt_detach(&iq->iq_ev);
+ evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
+ NULL, "arm_intr", name);
+
+ restore_interrupts(oldirqstate);
+
+ return(ih);
+}
+
+void
+arm_intr_disestablish(void *cookie)
+{
+ struct intrhand *ih = cookie;
+ struct intrq *iq = &arm_intrq[ih->ih_irq];
+ int oldirqstate;
+
+ oldirqstate = disable_interrupts(I32_bit);
+
+ TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
+
+ arm_intr_calculate_masks();
+
+ restore_interrupts(oldirqstate);
+ free(ih, M_DEVBUF);
+}
+
+/* called with external interrupts disabled */
+void
+arm_intr_dispatch(struct clockframe *frame)
+{
+ struct intrq *iq;
+ struct intrhand *ih;
+ int oldirqstate, pcpl, irq, ibit;
+ uint32_t hwpend;
+
+ pcpl = current_spl_level;
+
+ hwpend = arm_hardware_irq_status();
+
+ /*
+ * Disable all the interrupts that are pending. We will
+ * reenable them once they are processed and not masked.
+ */
+ intr_enabled &= ~hwpend;
+ arm_hardware_set_irq_mask(intr_enabled);
+
+ while (hwpend != 0) {
+ int intr_rc = 0;
+ irq = ffs(hwpend) - 1;
+ ibit = (1U << irq);
+
+ hwpend &= ~ibit;
+
+ if (arm_imask[pcpl] & ibit) {
+ /*
+ * IRQ is masked; mark it as pending and check
+ * the next one.
+ * The IRQ is already disabled by the currently running handler
+ */
+ arm_intr_pending |= ibit;
+ continue;
+ }
+
+ arm_intr_pending &= ~ibit;
+
+ iq = &arm_intrq[irq];
+ iq->iq_ev.ev_count++;
+ uvmexp.intrs++;
+ current_spl_level = iq->iq_ipl;
+ oldirqstate = enable_interrupts(I32_bit);
+ for (ih = TAILQ_FIRST(&iq->iq_list);
+ ((ih != NULL) && (intr_rc != 1));
+ ih = TAILQ_NEXT(ih, ih_list)) {
+ intr_rc = (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
+ }
+ restore_interrupts(oldirqstate);
+
+ current_spl_level = pcpl;
+
+ /* Re-enable this interrupt now that's it's cleared. */
+ intr_enabled |= ibit;
+ arm_hardware_set_irq_mask(intr_enabled);
+
+ /* also check for any new interrupts that may have occurred,
+ * that we can handle at this spl level */
+ hwpend |= (arm_intr_pending & ~arm_imask[pcpl]);
+ }
+
+ /* Check for pendings soft intrs. */
+ if (arm_soft_intr_pending & ~arm_simask[current_spl_level]) {
+ /*
+ * XXX this feels the wrong place to enable irqs, as some
+ * soft ints are higher priority than hardware irqs
+ */
+ oldirqstate = enable_interrupts(I32_bit);
+ arm_do_pending_soft_intr();
+ restore_interrupts(oldirqstate);
+ }
+}
Index: arm/conf/files.footbridge
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/conf/files.footbridge,v
retrieving revision 1.12
diff -u -p -r1.12 files.footbridge
--- arm/conf/files.footbridge 19 Sep 2006 10:05:32 -0000 1.12
+++ arm/conf/files.footbridge 7 Apr 2007 18:29:09 -0000
@@ -13,6 +13,7 @@ file arch/arm/arm32/irq_dispatch.S
file arch/arm/footbridge/footbridge_irqhandler.c footbridge
file arch/arm/footbridge/footbridge_clock.c footbridge
file arch/arm/arm/softintr.c footbridge
+file arch/arm/arm32/arm_irqhandler.c footbridge
# DC21285 "Footbridge" serial port
device fcom: tty, bus_space_generic
Index: arm/footbridge/footbridge_intr.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/footbridge/footbridge_intr.h,v
retrieving revision 1.10
diff -u -p -r1.10 footbridge_intr.h
--- arm/footbridge/footbridge_intr.h 9 Mar 2007 06:45:20 -0000 1.10
+++ arm/footbridge/footbridge_intr.h 7 Apr 2007 18:29:09 -0000
@@ -38,190 +38,14 @@
#ifndef _FOOTBRIDGE_INTR_H_
#define _FOOTBRIDGE_INTR_H_
-#include <arm/armreg.h>
+#include <arm/arm_intr.h>
-/* Define the various Interrupt Priority Levels */
+#define IST_UNUSABLE -1 /* interrupt cannot be used */
+#define IST_NONE 0 /* none (dummy) */
+#define IST_PULSE 1 /* pulsed */
+#define IST_EDGE 2 /* edge-triggered */
+#define IST_LEVEL 3 /* level-triggered */
-/* Hardware Interrupt Priority Levels are not mutually exclusive. */
-
-#define IPL_NONE 0 /* nothing */
-#define IPL_SOFT 1 /* generic soft interrupts */
-#define IPL_SOFTCLOCK 2 /* clock software interrupts */
-#define IPL_SOFTNET 3 /* network software interrupts */
-#define IPL_BIO 4 /* block I/O */
-#define IPL_NET 5 /* network */
-#define IPL_SOFTSERIAL 6 /* serial software interrupts */
-#define IPL_TTY 7 /* terminal */
-#define IPL_LPT IPL_TTY
-#define IPL_VM 8 /* memory allocation */
-#define IPL_AUDIO 9 /* audio */
-#define IPL_CLOCK 10 /* clock */
-#define IPL_STATCLOCK 11 /* statclock */
-#define IPL_HIGH 12 /* everything */
-#define IPL_SCHED IPL_HIGH
-#define IPL_LOCK IPL_HIGH
-#define IPL_SERIAL 13 /* serial */
-
-#define NIPL 14
-
-#define IST_UNUSABLE -1 /* interrupt cannot be used */
-#define IST_NONE 0 /* none (dummy) */
-#define IST_PULSE 1 /* pulsed */
-#define IST_EDGE 2 /* edge-triggered */
-#define IST_LEVEL 3 /* level-triggered */
-
-#define __NEWINTR /* enables new hooks in cpu_fork()/cpu_switch() */
-
-#define ARM_IRQ_HANDLER _C_LABEL(footbridge_intr_dispatch)
-
-#ifndef _LOCORE
-#include <arm/cpufunc.h>
-
-#include <arm/footbridge/dc21285mem.h>
-#include <arm/footbridge/dc21285reg.h>
-
-#define INT_SWMASK \
- ((1U << IRQ_SOFTINT) | (1U << IRQ_RESERVED0) | \
- (1U << IRQ_RESERVED1) | (1U << IRQ_RESERVED2))
-#define ICU_INT_HWMASK (0xffffffff & ~(INT_SWMASK | (1U << IRQ_RESERVED3)))
-
-/* only call this with interrupts off */
-static inline void __attribute__((__unused__))
- footbridge_set_intrmask(void)
-{
- extern volatile uint32_t intr_enabled;
- /* fetch once so we write the same number to both registers */
- uint32_t tmp = intr_enabled & ICU_INT_HWMASK;
-
- ((volatile uint32_t*)(DC21285_ARMCSR_VBASE))[IRQ_ENABLE_SET>>2] = tmp;
- ((volatile uint32_t*)(DC21285_ARMCSR_VBASE))[IRQ_ENABLE_CLEAR>>2] = ~tmp;
-}
-
-static inline void __attribute__((__unused__))
-footbridge_splx(int newspl)
-{
- extern volatile uint32_t intr_enabled;
- extern volatile int current_spl_level;
- extern volatile int footbridge_ipending;
- extern void footbridge_do_pending(void);
- int oldirqstate, hwpend;
-
- /* Don't let the compiler re-order this code with preceding code */
- __insn_barrier();
-
- current_spl_level = newspl;
-
- hwpend = (footbridge_ipending & ICU_INT_HWMASK) & ~newspl;
- if (hwpend != 0) {
- oldirqstate = disable_interrupts(I32_bit);
- intr_enabled |= hwpend;
- footbridge_set_intrmask();
- restore_interrupts(oldirqstate);
- }
-
- if ((footbridge_ipending & INT_SWMASK) & ~newspl)
- footbridge_do_pending();
-}
-
-static inline int __attribute__((__unused__))
-footbridge_splraise(int ipl)
-{
- extern volatile int current_spl_level;
- extern int footbridge_imask[];
- int old;
-
- old = current_spl_level;
- current_spl_level |= footbridge_imask[ipl];
-
- /* Don't let the compiler re-order this code with subsequent code */
- __insn_barrier();
-
- return (old);
-}
-
-static inline int __attribute__((__unused__))
-footbridge_spllower(int ipl)
-{
- extern volatile int current_spl_level;
- extern int footbridge_imask[];
- int old = current_spl_level;
-
- footbridge_splx(footbridge_imask[ipl]);
- return(old);
-}
-
-/* should only be defined in footbridge_intr.c */
-#if !defined(ARM_SPL_NOINLINE)
-
-#define splx(newspl) footbridge_splx(newspl)
-#define _spllower(ipl) footbridge_spllower(ipl)
-#define _splraise(ipl) footbridge_splraise(ipl)
-void _setsoftintr(int);
-
-#else
-
-int _splraise(int);
-int _spllower(int);
-void splx(int);
-void _setsoftintr(int);
-
-#endif /* ! ARM_SPL_NOINLINE */
-
-#include <sys/device.h>
-#include <sys/queue.h>
-#include <machine/irqhandler.h>
-
-#define splsoft() _splraise(IPL_SOFT)
-
-#define spl0() (void)_spllower(IPL_NONE)
-#define spllowersoftclock() (void)_spllower(IPL_SOFTCLOCK)
-
-typedef uint8_t ipl_t;
-typedef struct {
- ipl_t _ipl;
-} ipl_cookie_t;
-
-static inline ipl_cookie_t
-makeiplcookie(ipl_t ipl)
-{
-
- return (ipl_cookie_t){._ipl = ipl};
-}
-
-static inline int
-splraiseipl(ipl_cookie_t icookie)
-{
-
- return _splraise(icookie._ipl);
-}
-
-#include <sys/spl.h>
-
-/* Use generic software interrupt support. */
-#include <arm/softintr.h>
-
-/* footbridge has 32 interrupt lines */
-#define NIRQ 32
-
-struct intrhand {
- TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
- int (*ih_func)(void *); /* handler */
- void *ih_arg; /* arg for handler */
- int ih_ipl; /* IPL_* */
- int ih_irq; /* IRQ number */
-};
-
-#define IRQNAMESIZE sizeof("footbridge irq 31")
-
-struct intrq {
- TAILQ_HEAD(, intrhand) iq_list; /* handler list */
- struct evcnt iq_ev; /* event counter */
- int iq_mask; /* IRQs to mask while handling */
- int iq_levels; /* IPL_*'s this IRQ has */
- int iq_ist; /* share type */
- char iq_name[IRQNAMESIZE]; /* interrupt name */
-};
-
-#endif /* _LOCORE */
+#define FOOTBRIDGE_NIRQ 32 /* 32bits in the irq mask */
#endif /* _FOOTBRIDGE_INTR_H */
Index: arm/footbridge/footbridge_intr_hardware.h
===================================================================
RCS file: arm/footbridge/footbridge_intr_hardware.h
diff -N arm/footbridge/footbridge_intr_hardware.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ arm/footbridge/footbridge_intr_hardware.h 7 Apr 2007 18:29:09 -0000
@@ -0,0 +1,51 @@
+/* $NetBSD: $ */
+
+/*
+ * Copyright (c) 2007 Christopher Gilbert
+ * All rights reserved.
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the company nor the name of the author may be used to
+ * endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _FOOTBRIDGE_INTR_HARDWARE_H_
+#define _FOOTBRIDGE_INTR_HARDWARE_H_
+
+#ifndef _LOCORE
+
+#include <arm/footbridge/dc21285mem.h>
+#include <arm/footbridge/dc21285reg.h>
+
+
+static inline void __attribute__((__unused__))
+ arm_hardware_set_irq_mask(uint32_t intr_enabled)
+{
+ ((volatile uint32_t*)(DC21285_ARMCSR_VBASE))[IRQ_ENABLE_SET>>2] = intr_enabled;
+ ((volatile uint32_t*)(DC21285_ARMCSR_VBASE))[IRQ_ENABLE_CLEAR>>2] = ~intr_enabled;
+}
+static inline uint32_t __attribute__((__unused__))
+ arm_hardware_irq_status(void)
+{
+ return ((volatile uint32_t*)(DC21285_ARMCSR_VBASE))[IRQ_STATUS>>2];
+}
+
+#endif
+#endif /* _FOOTBRIDGE_INTR_HARDWARE_H */
Index: arm/footbridge/footbridge_irqhandler.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/footbridge/footbridge_irqhandler.c,v
retrieving revision 1.17
diff -u -p -r1.17 footbridge_irqhandler.c
--- arm/footbridge/footbridge_irqhandler.c 25 Dec 2006 18:39:48 -0000 1.17
+++ arm/footbridge/footbridge_irqhandler.c 7 Apr 2007 18:29:09 -0000
@@ -51,59 +51,14 @@ __KERNEL_RCSID(0,"$NetBSD: footbridge_ir
#include <machine/intr.h>
#include <machine/cpu.h>
-#include <arm/footbridge/dc21285mem.h>
-#include <arm/footbridge/dc21285reg.h>
-
+#include <arm/arm_intr.h>
+#include <arm/footbridge/footbridge_irqhandler.h>
#include <dev/pci/pcivar.h>
-#include "isa.h"
-#if NISA > 0
-#include <dev/isa/isavar.h>
-#endif
-
-/* Interrupt handler queues. */
-static struct intrq footbridge_intrq[NIRQ];
-
-/* Interrupts to mask at each level. */
-int footbridge_imask[NIPL];
-
-/* Software copy of the IRQs we have enabled. */
-volatile uint32_t intr_enabled;
-
-/* Current interrupt priority level */
-volatile int current_spl_level;
-
-/* Interrupts pending */
-volatile int footbridge_ipending;
-
-void footbridge_intr_dispatch(struct clockframe *frame);
-
const struct evcnt *footbridge_pci_intr_evcnt __P((void *, pci_intr_handle_t));
-void footbridge_do_pending(void);
-
-static const uint32_t si_to_irqbit[SI_NQUEUES] =
- { IRQ_SOFTINT,
- IRQ_RESERVED0,
- IRQ_RESERVED1,
- IRQ_RESERVED2 };
-
-#define SI_TO_IRQBIT(si) (1U << si_to_irqbit[(si)])
-
-/*
- * Map a software interrupt queue to an interrupt priority level.
- */
-static const int si_to_ipl[SI_NQUEUES] = {
- IPL_SOFT, /* SI_SOFT */
- IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
- IPL_SOFTNET, /* SI_SOFTNET */
- IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
-};
-
const struct evcnt *
-footbridge_pci_intr_evcnt(pcv, ih)
- void *pcv;
- pci_intr_handle_t ih;
+footbridge_pci_intr_evcnt(void *pcv, pci_intr_handle_t ih)
{
/* XXX check range is valid */
#if NISA > 0
@@ -111,356 +66,26 @@ footbridge_pci_intr_evcnt(pcv, ih)
return isa_intr_evcnt(NULL, (ih & 0x0f));
}
#endif
- return &footbridge_intrq[ih].iq_ev;
-}
-
-static inline void
-footbridge_enable_irq(int irq)
-{
- intr_enabled |= (1U << irq);
-
- footbridge_set_intrmask();
-}
-
-static inline void
-footbridge_disable_irq(int irq)
-{
- intr_enabled &= ~(1U << irq);
- footbridge_set_intrmask();
-}
-
-/*
- * NOTE: This routine must be called with interrupts disabled in the CPSR.
- */
-static void
-footbridge_intr_calculate_masks(void)
-{
- struct intrq *iq;
- struct intrhand *ih;
- int irq, ipl;
-
- /* First, figure out which IPLs each IRQ has. */
- for (irq = 0; irq < NIRQ; irq++) {
- int levels = 0;
- iq = &footbridge_intrq[irq];
- footbridge_disable_irq(irq);
- for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
- ih = TAILQ_NEXT(ih, ih_list))
- levels |= (1U << ih->ih_ipl);
- iq->iq_levels = levels;
- }
-
- /* Next, figure out which IRQs are used by each IPL. */
- for (ipl = 0; ipl < NIPL; ipl++) {
- int irqs = 0;
- for (irq = 0; irq < NIRQ; irq++) {
- if (footbridge_intrq[irq].iq_levels & (1U << ipl))
- irqs |= (1U << irq);
- }
- footbridge_imask[ipl] = irqs;
- }
-
- /* IPL_NONE must open up all interrupts */
- footbridge_imask[IPL_NONE] = 0;
-
- /*
- * Initialize the soft interrupt masks to block themselves.
- */
- footbridge_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFT);
- footbridge_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTCLOCK);
- footbridge_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTNET);
- footbridge_imask[IPL_SOFTSERIAL] = SI_TO_IRQBIT(SI_SOFTSERIAL);
-
- footbridge_imask[IPL_SOFTCLOCK] |= footbridge_imask[IPL_SOFT];
- footbridge_imask[IPL_SOFTNET] |= footbridge_imask[IPL_SOFTCLOCK];
-
- /*
- * Enforce a hierarchy that gives "slow" device (or devices with
- * limited input buffer space/"real-time" requirements) a better
- * chance at not dropping data.
- */
- footbridge_imask[IPL_BIO] |= footbridge_imask[IPL_SOFTNET];
- footbridge_imask[IPL_NET] |= footbridge_imask[IPL_BIO];
- footbridge_imask[IPL_SOFTSERIAL] |= footbridge_imask[IPL_NET];
-
- footbridge_imask[IPL_TTY] |= footbridge_imask[IPL_SOFTSERIAL];
-
- /*
- * splvm() blocks all interrupts that use the kernel memory
- * allocation facilities.
- */
- footbridge_imask[IPL_VM] |= footbridge_imask[IPL_TTY];
-
- /*
- * Audio devices are not allowed to perform memory allocation
- * in their interrupt routines, and they have fairly "real-time"
- * requirements, so give them a high interrupt priority.
- */
- footbridge_imask[IPL_AUDIO] |= footbridge_imask[IPL_VM];
-
- /*
- * splclock() must block anything that uses the scheduler.
- */
- footbridge_imask[IPL_CLOCK] |= footbridge_imask[IPL_AUDIO];
-
- /*
- * footbridge has separate statclock.
- */
- footbridge_imask[IPL_STATCLOCK] |= footbridge_imask[IPL_CLOCK];
-
- /*
- * splhigh() must block "everything".
- */
- footbridge_imask[IPL_HIGH] |= footbridge_imask[IPL_STATCLOCK];
-
- /*
- * XXX We need serial drivers to run at the absolute highest priority
- * in order to avoid overruns, so serial > high.
- */
- footbridge_imask[IPL_SERIAL] |= footbridge_imask[IPL_HIGH];
-
- /*
- * Calculate the ipl level to go to when handling this interrupt
- */
- for (irq = 0; irq < NIRQ; irq++) {
- int irqs = (1U << irq);
- iq = &footbridge_intrq[irq];
- if (TAILQ_FIRST(&iq->iq_list) != NULL)
- footbridge_enable_irq(irq);
- for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
- ih = TAILQ_NEXT(ih, ih_list))
- irqs |= footbridge_imask[ih->ih_ipl];
- iq->iq_mask = irqs;
- }
-}
-
-int
-_splraise(int ipl)
-{
- return (footbridge_splraise(ipl));
-}
-
-/* this will always take us to the ipl passed in */
-void
-splx(int new)
-{
- footbridge_splx(new);
-}
-
-int
-_spllower(int ipl)
-{
- return (footbridge_spllower(ipl));
-}
-
-void
-footbridge_do_pending(void)
-{
- static __cpu_simple_lock_t processing = __SIMPLELOCK_UNLOCKED;
- uint32_t new, oldirqstate;
-
- if (__cpu_simple_lock_try(&processing) == 0)
- return;
-
- new = current_spl_level;
-
- oldirqstate = disable_interrupts(I32_bit);
-
-#define DO_SOFTINT(si) \
- if ((footbridge_ipending & ~new) & SI_TO_IRQBIT(si)) { \
- footbridge_ipending &= ~SI_TO_IRQBIT(si); \
- current_spl_level |= footbridge_imask[si_to_ipl[(si)]]; \
- restore_interrupts(oldirqstate); \
- softintr_dispatch(si); \
- oldirqstate = disable_interrupts(I32_bit); \
- current_spl_level = new; \
- }
- DO_SOFTINT(SI_SOFTSERIAL);
- DO_SOFTINT(SI_SOFTNET);
- DO_SOFTINT(SI_SOFTCLOCK);
- DO_SOFTINT(SI_SOFT);
-
- __cpu_simple_unlock(&processing);
-
- restore_interrupts(oldirqstate);
-}
-
-
-/* called from splhigh, so the matching splx will set the interrupt up.*/
-void
-_setsoftintr(int si)
-{
- int oldirqstate;
-
- oldirqstate = disable_interrupts(I32_bit);
- footbridge_ipending |= SI_TO_IRQBIT(si);
- restore_interrupts(oldirqstate);
-
- /* Process unmasked pending soft interrupts. */
- if ((footbridge_ipending & INT_SWMASK) & ~current_spl_level)
- footbridge_do_pending();
+ return arm_intr_evcnt(ih);
}
void
footbridge_intr_init(void)
{
- struct intrq *iq;
- int i;
-
- intr_enabled = 0;
- current_spl_level = 0xffffffff;
- footbridge_ipending = 0;
- footbridge_set_intrmask();
-
- for (i = 0; i < NIRQ; i++) {
- iq = &footbridge_intrq[i];
- TAILQ_INIT(&iq->iq_list);
-
- sprintf(iq->iq_name, "irq %d", i);
- evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
- NULL, "footbridge", iq->iq_name);
- }
-
- footbridge_intr_calculate_masks();
-
- /* Enable IRQ's, we don't have any FIQ's*/
- enable_interrupts(I32_bit);
+ return arm_intr_init();
}
void *
footbridge_intr_claim(int irq, int ipl, const char *name, int (*func)(void *), void *arg)
{
- struct intrq *iq;
- struct intrhand *ih;
- u_int oldirqstate;
-
- if (irq < 0 || irq > NIRQ)
+ if (irq < 0 || irq > FOOTBRIDGE_NIRQ)
panic("footbridge_intr_establish: IRQ %d out of range", irq);
- ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
- if (ih == NULL)
- {
- printf("No memory");
- return (NULL);
- }
-
- ih->ih_func = func;
- ih->ih_arg = arg;
- ih->ih_ipl = ipl;
- ih->ih_irq = irq;
-
- iq = &footbridge_intrq[irq];
-
- iq->iq_ist = IST_LEVEL;
-
- oldirqstate = disable_interrupts(I32_bit);
-
- TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
-
- footbridge_intr_calculate_masks();
-
- /* detach the existing event counter and add the new name */
- evcnt_detach(&iq->iq_ev);
- evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
- NULL, "footbridge", name);
-
- restore_interrupts(oldirqstate);
-
- return(ih);
+ return arm_intr_claim(irq, ipl, name, func, arg);
}
void
footbridge_intr_disestablish(void *cookie)
{
- struct intrhand *ih = cookie;
- struct intrq *iq = &footbridge_intrq[ih->ih_irq];
- int oldirqstate;
-
- /* XXX need to free ih ? */
- oldirqstate = disable_interrupts(I32_bit);
-
- TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
-
- footbridge_intr_calculate_masks();
-
- restore_interrupts(oldirqstate);
-}
-
-static uint32_t footbridge_intstatus(void);
-
-static inline uint32_t footbridge_intstatus()
-{
- return ((volatile uint32_t*)(DC21285_ARMCSR_VBASE))[IRQ_STATUS>>2];
-}
-
-/* called with external interrupts disabled */
-void
-footbridge_intr_dispatch(struct clockframe *frame)
-{
- struct intrq *iq;
- struct intrhand *ih;
- int oldirqstate, pcpl, irq, ibit, hwpend;
-
- pcpl = current_spl_level;
-
- hwpend = footbridge_intstatus();
-
- /*
- * Disable all the interrupts that are pending. We will
- * reenable them once they are processed and not masked.
- */
- intr_enabled &= ~hwpend;
- footbridge_set_intrmask();
-
- while (hwpend != 0) {
- int intr_rc = 0;
- irq = ffs(hwpend) - 1;
- ibit = (1U << irq);
-
- hwpend &= ~ibit;
-
- if (pcpl & ibit) {
- /*
- * IRQ is masked; mark it as pending and check
- * the next one. Note: the IRQ is already disabled.
- */
- footbridge_ipending |= ibit;
- continue;
- }
-
- footbridge_ipending &= ~ibit;
-
- iq = &footbridge_intrq[irq];
- iq->iq_ev.ev_count++;
- uvmexp.intrs++;
- current_spl_level |= iq->iq_mask;
- oldirqstate = enable_interrupts(I32_bit);
- for (ih = TAILQ_FIRST(&iq->iq_list);
- ((ih != NULL) && (intr_rc != 1));
- ih = TAILQ_NEXT(ih, ih_list)) {
- intr_rc = (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
- }
- restore_interrupts(oldirqstate);
-
- current_spl_level = pcpl;
-
- /* Re-enable this interrupt now that's it's cleared. */
- intr_enabled |= ibit;
- footbridge_set_intrmask();
-
- /* also check for any new interrupts that may have occurred,
- * that we can handle at this spl level */
- hwpend |= (footbridge_ipending & ICU_INT_HWMASK) & ~pcpl;
- }
-
- /* Check for pendings soft intrs. */
- if ((footbridge_ipending & INT_SWMASK) & ~current_spl_level) {
- /*
- * XXX this feels the wrong place to enable irqs, as some
- * soft ints are higher priority than hardware irqs
- */
- oldirqstate = enable_interrupts(I32_bit);
- footbridge_do_pending();
- restore_interrupts(oldirqstate);
- }
+ return arm_intr_disestablish(cookie);
}
Index: arm/include/Makefile
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/include/Makefile,v
retrieving revision 1.34
diff -u -p -r1.34 Makefile
--- arm/include/Makefile 18 Feb 2007 15:53:55 -0000 1.34
+++ arm/include/Makefile 7 Apr 2007 18:29:09 -0000
@@ -2,7 +2,7 @@
INCSDIR= /usr/include/arm
-INCS= ansi.h aout_machdep.h armreg.h asm.h atomic.h \
+INCS= ansi.h aout_machdep.h arm_intr.h armreg.h asm.h atomic.h \
bswap.h byte_swap.h bus.h \
cdefs.h cpu.h \
disklabel.h \
Index: arm/include/arm_intr.h
===================================================================
RCS file: arm/include/arm_intr.h
diff -N arm/include/arm_intr.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ arm/include/arm_intr.h 7 Apr 2007 18:29:09 -0000
@@ -0,0 +1,214 @@
+/* $NetBSD: footbridge_intr.h,v 1.10 2007/03/09 06:45:20 thorpej Exp $ */
+
+/*
+ * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
+ * All rights reserved.
+ *
+ * Written by Jason R. Thorpe for Wasabi Systems, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed for the NetBSD Project by
+ * Wasabi Systems, Inc.
+ * 4. The name of Wasabi Systems, Inc. may not be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _ARM_INTR_H_
+#define _ARM_INTR_H_
+
+#include <arm/armreg.h>
+
+/* Define the various Interrupt Priority Levels */
+
+/* Hardware Interrupt Priority Levels are not mutually exclusive. */
+
+#define IPL_NONE 0 /* nothing */
+#define IPL_SOFT 1 /* generic soft interrupts */
+#define IPL_SOFTCLOCK 2 /* clock software interrupts */
+#define IPL_SOFTNET 3 /* network software interrupts */
+#define IPL_BIO 4 /* block I/O */
+#define IPL_NET 5 /* network */
+#define IPL_SOFTSERIAL 6 /* serial software interrupts */
+#define IPL_TTY 7 /* terminal */
+#define IPL_LPT IPL_TTY
+#define IPL_VM 8 /* memory allocation */
+#define IPL_AUDIO 9 /* audio */
+#define IPL_CLOCK 10 /* clock */
+#define IPL_STATCLOCK 11 /* statclock */
+#define IPL_HIGH 12 /* everything */
+#define IPL_SCHED IPL_HIGH
+#define IPL_LOCK IPL_HIGH
+#define IPL_SERIAL 13 /* serial */
+
+#define NIPL 14
+
+#define __NEWINTR /* enables new hooks in cpu_fork()/cpu_switch() */
+
+#define ARM_IRQ_HANDLER _C_LABEL(arm_intr_dispatch)
+
+#ifndef _LOCORE
+#include <arm/cpufunc.h>
+#include <machine/intr_hardware.h>
+
+static inline void __attribute__((__unused__))
+arm_intr_splx(int newspl)
+{
+ extern volatile uint32_t intr_enabled;
+ extern volatile int current_spl_level;
+ extern volatile uint32_t arm_intr_pending;
+ extern void arm_do_pending_soft_intr(void);
+ extern uint32_t arm_imask[NIPL];
+ extern uint32_t arm_simask[NIPL];
+ extern volatile uint32_t arm_soft_intr_pending;
+ int oldirqstate, hwpend;
+
+ /* Don't let the compiler re-order this code with preceding code */
+ __insn_barrier();
+
+ current_spl_level = newspl;
+
+ /* un-mask any interupts that we can now handle */
+ hwpend = (arm_intr_pending & ~arm_imask[newspl]);
+ if (hwpend != 0) {
+ oldirqstate = disable_interrupts(I32_bit);
+ intr_enabled |= hwpend;
+ arm_hardware_set_irq_mask(intr_enabled);
+ restore_interrupts(oldirqstate);
+ }
+
+ if (arm_soft_intr_pending & ~arm_simask[newspl])
+ arm_do_pending_soft_intr();
+}
+
+static inline int __attribute__((__unused__))
+arm_intr_splraise(int ipl)
+{
+ extern volatile int current_spl_level;
+ int old;
+
+ old = current_spl_level;
+ current_spl_level = ipl;
+
+ /* Don't let the compiler re-order this code with subsequent code */
+ __insn_barrier();
+
+ return (old);
+}
+
+static inline int __attribute__((__unused__))
+arm_intr_spllower(int ipl)
+{
+ extern volatile int current_spl_level;
+ int old = current_spl_level;
+
+ arm_intr_splx(ipl);
+ return(old);
+}
+
+/* should only be defined in footbridge_intr.c */
+#if !defined(ARM_SPL_NOINLINE)
+
+#define splx(newspl) arm_intr_splx(newspl)
+#define _spllower(ipl) arm_intr_spllower(ipl)
+#define _splraise(ipl) arm_intr_splraise(ipl)
+void _setsoftintr(int);
+
+#else
+
+int _splraise(int);
+int _spllower(int);
+void splx(int);
+void _setsoftintr(int);
+
+#endif /* ! ARM_SPL_NOINLINE */
+
+/* public apis in arm_irqhandler.c*/
+void arm_intr_init(void);
+void *
+arm_intr_claim(int irq, int ipl, const char *name, int (*func)(void *), void *arg);
+void arm_intr_disestablish(void *cookie);
+
+const struct evcnt * arm_intr_evcnt(int ih);
+
+
+#include <sys/device.h>
+#include <sys/queue.h>
+#include <machine/irqhandler.h>
+
+#define splsoft() _splraise(IPL_SOFT)
+
+#define spl0() (void)_spllower(IPL_NONE)
+#define spllowersoftclock() (void)_spllower(IPL_SOFTCLOCK)
+
+typedef uint8_t ipl_t;
+typedef struct {
+ ipl_t _ipl;
+} ipl_cookie_t;
+
+static inline ipl_cookie_t
+makeiplcookie(ipl_t ipl)
+{
+
+ return (ipl_cookie_t){._ipl = ipl};
+}
+
+static inline int
+splraiseipl(ipl_cookie_t icookie)
+{
+
+ return _splraise(icookie._ipl);
+}
+
+#include <sys/spl.h>
+
+/* Use generic software interrupt support. */
+#include <arm/softintr.h>
+
+/* arm_intr handles 32 interrupt lines */
+#define ARM_INTR_NIRQ 32
+
+struct intrhand {
+ TAILQ_ENTRY(intrhand) ih_list; /* link on intrq list */
+ int (*ih_func)(void *); /* handler */
+ void *ih_arg; /* arg for handler */
+ int ih_ipl; /* IPL_* */
+ int ih_irq; /* IRQ number */
+};
+
+#define IRQNAMESIZE sizeof("arm_intr irq 31")
+
+struct intrq {
+ TAILQ_HEAD(, intrhand) iq_list; /* handler list */
+ struct evcnt iq_ev; /* event counter */
+ int iq_mask; /* IRQs to mask while handling */
+ int iq_levels; /* IPL_*'s this IRQ has */
+ int iq_ipl; /* highest ipl this IRQ has */
+ int iq_ist; /* share type */
+ char iq_name[IRQNAMESIZE]; /* interrupt name */
+};
+
+#endif /* _LOCORE */
+
+#endif /* _ARM_INTR_H */
Index: cats/cats/autoconf.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cats/cats/autoconf.c,v
retrieving revision 1.10
diff -u -p -r1.10 autoconf.c
--- cats/cats/autoconf.c 11 Dec 2005 12:17:04 -0000 1.10
+++ cats/cats/autoconf.c 7 Apr 2007 18:29:10 -0000
@@ -133,7 +133,7 @@ cpu_rootconf(void)
* Configure all the root devices
* The root devices are expected to configure their own children
*/
-extern int footbridge_imask[NIPL];
+extern uint32_t arm_imask[NIPL];
void
cpu_configure(void)
@@ -153,11 +153,11 @@ cpu_configure(void)
/* Debugging information */
#ifndef TERSE
printf("ipl_bio=%08x ipl_net=%08x ipl_tty=%08x ipl_vm=%08x\n",
- footbridge_imask[IPL_BIO], footbridge_imask[IPL_NET],
- footbridge_imask[IPL_TTY], footbridge_imask[IPL_VM]);
+ arm_imask[IPL_BIO], arm_imask[IPL_NET],
+ arm_imask[IPL_TTY], arm_imask[IPL_VM]);
printf("ipl_audio=%08x ipl_imp=%08x ipl_high=%08x ipl_serial=%08x\n",
- footbridge_imask[IPL_AUDIO], footbridge_imask[IPL_CLOCK],
- footbridge_imask[IPL_HIGH], footbridge_imask[IPL_SERIAL]);
+ arm_imask[IPL_AUDIO], arm_imask[IPL_CLOCK],
+ arm_imask[IPL_HIGH], arm_imask[IPL_SERIAL]);
#endif
/* Time to start taking interrupts so lets open the flood gates .... */
Index: cats/include/Makefile
===================================================================
RCS file: /cvsroot/src/sys/arch/cats/include/Makefile,v
retrieving revision 1.21
diff -u -p -r1.21 Makefile
--- cats/include/Makefile 9 Feb 2007 21:55:02 -0000 1.21
+++ cats/include/Makefile 7 Apr 2007 18:29:10 -0000
@@ -10,7 +10,7 @@ INCS= ansi.h aout_machdep.h asm.h \
float.h fp.h frame.h \
ieee.h ieeefp.h \
int_const.h int_fmtio.h int_limits.h int_mwgwtypes.h int_types.h \
- intr.h ipkdb.h \
+ intr.h intr_hardware.h ipkdb.h \
limits.h lock.h \
math.h mcontext.h mutex.h \
param.h pcb.h pmap.h pmc.h proc.h profile.h ptrace.h \
Index: cats/include/intr_hardware.h
===================================================================
RCS file: cats/include/intr_hardware.h
diff -N cats/include/intr_hardware.h
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ cats/include/intr_hardware.h 7 Apr 2007 18:29:10 -0000
@@ -0,0 +1,3 @@
+/* $NetBSD: intr.h,v 1.5 2002/09/28 15:53:03 chris Exp $ */
+
+#include <arm/footbridge/footbridge_intr_hardware.h>
--------------080701050503080102070009--