Subject: Re: Debugging / SPL-levels / AT91RM9200 success
To: None <email@example.com>
From: Toru Nishimura <firstname.lastname@example.org>
Date: 03/07/2007 10:16:21
Sorry for segmented littering replies. This'd be the last...
> As you already wonder I suspect GPIO/IRQ "line fiddling" ends up with
> failing to catch or forgetting interrupt notification with your case.
Another concern is that the GPIO machinery can not keep up pace for
external events, that is, low latency quick response for higher frequency
domain. I once stepped across the story telling some ARM7 SoC GPIO
are so slow that not able to use for high speed bit-bang, "high speed"
in a sense where as fast as CPU core or external devices can run. The
designer's solution was to add another GPIO circuit and release revised
products (it's always good to announce new arrival!)
Toru Nishimura/ALKYL Technology