Subject: Re: Re: OMAP _almost_ builds at tip of tree now.
To: None <>
From: Toru Nishimura <>
List: port-arm
Date: 02/22/2007 04:09:52
Bucky Katz wrote;

> It's not unusual on ARM embedded systems to have > 32 interrupts, as
> GPIOs can be configured to generate interrupts and hardware guys love
> to use GPIOs for signalling.

Yes, some ARM designers persuade many external interrupt line as possible.
MMSP2, made by a Korean company and used in GP2X game console, is so
flexible that it can configure/select the usage of most of the SoC pins and
make them external interrupt source.  (MC9328 and probably many MPC
variations have common approachs.)  I invented a concise way to describe
pin function selection as follows;

        altfn('A', "11111111", "11111111");
        altfn('B', "11111111", "1111ooxx");
        altfn('C', "iiiiiiii", "11111111");
        altfn('D', "xxiii111", "ii1o1i11");
        altfn('E', "11111111", "11111111");
        altfn('F', "xxxxxx11", "11111111");
        altfn('G', "11111111", "11111111");
        altfn('H', "xxxxxxxx", "xi1ooooo");
        altfn('I', "1i111111", "1111ii11");
        altfn('J', "ioo11111", "11111111");
        altfn('K', "xxxxxxxx", "ii1iii1i");
        altfn('L', "xxxxI111", "11111111");
        altfn('M', "xxxxxxxx", "iiiiiiii");
        altfn('N', "xxxxxxxx", "xxxxxxxx");
        altfn('O', "xxxxxxxx", "xxxxxxxx");

The SoC names pins A0..15, B0..15 and so on.  Here "io12Ix" is the
designation of pin function among input sense, output control, alt1, alt2,
interrupt source and don't-care/not-wired.  The SoC provides a
convenience registers to identify interrupt source bit position in a simple
manner.  It's rather comforting to know the CPU core interrupt notification
register itself is a painless standard 32bit design.

Toru Nishimura/ALKYL Technology