Subject: Re: Low Power Arm Board
To: None <>
From: Toru Nishimura <>
List: port-arm
Date: 09/17/2006 09:49:34
Brian Rose asked;

> Also, if a chip has an ARM9 core, how much work is it to port NetBSD to 
> it? If I end up designing my own boards, I am looking at some new 
> processors that are just coming out.

Porting NetBSD to ARM is an easy task.  NetBSD MI (machine independent
part) is fairly complete and you need not to dig deep to grasp how it works.

- The hardest part of porting effort to understand the target ARM SoC
address space.  ARM SoC has wide varieties among where resides and how
handles RAM and NOR Flash memory.  The common arrangement is
to have vaddr 0xC000'0000 for kernel and to populate SoC devices in
somewhere high range, say, vaddr 0xD000'0000 - 0xF000'0000.  The
latter can be done with a simple array of pmap_devmap[].

- control transition from bootloader to NetBSD is always pain since
it's common that vaddr arrangement of bootloader disagrees with
what NetBSD expects.  This may end up with large amount of sweat
and time to be spent before completing init_arm().  Every single line
of code must be well understood.  That's the most significant part.

- Working UART is an important debugging tool.  It must be done
the first.  Polling UART is as simple as;

struct consdev xxcomcons = {
        NULL, NULL, xxcomcngetc, xxcomcnputc, xxcomcnpollc, NULL,
cn_tab = &xxcomcons;

Never attempt to play bus_space dance. UART address is constant
and well known.

- Some ARM SoC provide 64 interrupt sources.  It would complicate
MD interrupt machinery badly.  Prioritized (level to inhibit others)
control should make the logic simpler.

- UART in some ARM SoC has multiple interrupt sources for Tx/Rx
events.  It's supposed to implement independent controlling thread
(task in Linux term), however, not very useful in fact since popular
UART device driver (serial_core or other) assumes single interrupt
source for every event and HW circuit which doest not allow
simultaneous Tx/Rx.  In reality UART interrupt sources must be
aggregated into a single interrupt source and dispatched later to
simulate a single threaded UART HW.

Toru Nishimura/ALKYL Technology